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Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
[oweals/u-boot.git]
/
drivers
/
ddr
/
fsl
/
mpc85xx_ddr_gen3.c
diff --git
a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 6752d4d29e0861140fac00b946765898e86858d1..ab8d2deaf9f490d1e53a7ea25d454a7e94815fa9 100644
(file)
--- a/
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@
-1,15
+1,14
@@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
*/
#include <common.h>
+#include <log.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
+#include <linux/delay.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@
-46,17
+45,17
@@
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_
NUM_DDR_CONTROLLE
RS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_
SYS_NUM_DDR_CTL
RS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_
NUM_DDR_CONTROLLE
RS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_
SYS_NUM_DDR_CTL
RS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_
NUM_DDR_CONTROLLE
RS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_
SYS_NUM_DDR_CTL
RS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@
-176,9
+175,6
@@
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
-#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
- out_be32(&ddr->debug[28], 0x30003000);
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);