-/* MarkW: how should these base addresses be done for A-V? */
-#define BASE_PTR_MGR 0x00040000
-#define BASE_SCC_MGR 0x00058000
-#define BASE_REG_FILE 0x00070000
-#define BASE_TIMER 0x00078000
-#define BASE_PHY_MGR 0x00088000
-#define BASE_RW_MGR 0x00090000
-#define BASE_DATA_MGR 0x00098000
-#define BASE_MMR 0x000C0000
-#define BASE_TRK_MGR 0x000D0000
-
-#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
-#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
-#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
-#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
-#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
-#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
-#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
-#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
+#define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
+#define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
+#define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
+#define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
+#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
+#define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
+#define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
+#define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900