*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
* Jason Jin <Jason.jin@freescale.com>
*
*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
* Jason Jin <Jason.jin@freescale.com>
*
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
/* Macros to read and write values to x86 emulator memory. Memory is always
* considered to be little endian, so we use macros to do endian swapping
/* Macros to read and write values to x86 emulator memory. Memory is always
* considered to be little endian, so we use macros to do endian swapping
-#define readb_le(base) *((u8*)(base))
-#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
-#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
- ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
+#define readb_le(base) *((u8*)(base))
+#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
+#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
+ ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
-#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
- writeb_le(base + 1, (v >> 8) & 0xff)
-#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
- writeb_le(base + 1, (v >> 8) & 0xff), \
- writeb_le(base + 2, (v >> 16) & 0xff), \
- writeb_le(base + 3, (v >> 24) & 0xff)
+#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
+ writeb_le(base + 1, (v >> 8) & 0xff)
+#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
+ writeb_le(base + 1, (v >> 8) & 0xff), \
+ writeb_le(base + 2, (v >> 16) & 0xff), \
+ writeb_le(base + 3, (v >> 24) & 0xff)
-#define readb_le(base) *((u8*)(base))
-#define readw_le(base) *((u16*)(base))
-#define readl_le(base) *((u32*)(base))
+#define readb_le(base) *((u8*)(base))
+#define readw_le(base) *((u16*)(base))
+#define readl_le(base) *((u32*)(base))
#define writeb_le(base, v) *((u8*)(base)) = (v)
#define writew_le(base, v) *((u16*)(base)) = (v)
#define writel_le(base, v) *((u32*)(base)) = (v)
#define writeb_le(base, v) *((u8*)(base)) = (v)
#define writew_le(base, v) *((u16*)(base)) = (v)
#define writel_le(base, v) *((u32*)(base)) = (v)
-type - Type of port access (1 = byte, 2 = word, 3 = dword)
-defVal - Default power on value
+type - Type of port access (1 = byte, 2 = word, 3 = dword)
+defVal - Default power on value