- out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (UART0_BASE + UART_LSR); /* clear line status */
- val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
- out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
-
+#if defined(CONFIG_SERIAL_MULTI)
+ out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
+ out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+ out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
+ out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8 (dev_base + UART_LSR); /* clear line status */
+ val = in8 (dev_base + UART_RBR); /* read receive buffer */
+ out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
+ out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
+#else
+ out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+ out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
+ val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
+ out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+#endif