+ return 0;
+}
+
+static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
+{
+ u32 emac_reg;
+ u32 sta_reg;
+
+ emac_reg = miiphy_getemac_offset(addr);
+
+ /* wait for completion */
+ if (emac_miiphy_wait(emac_reg) != 0)
+ return -1;
+
+ sta_reg = reg; /* reg address */
+
+ /* set clock (50MHz) and read flags */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_405EX)
+#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
+ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
+#else
+ sta_reg |= cmd;
+#endif
+#else
+ sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+ /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+ sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
+ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
+ if (cmd == EMAC_STACR_WRITE)
+ memcpy(&sta_reg, &value, 2); /* put in data */
+
+ out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
+ debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
+
+ /* wait for completion */
+ if (emac_miiphy_wait(emac_reg) != 0)
+ return -1;
+
+ debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);