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move L2 cache enable/disable function to cache.c in the omap3 SoC directory
[oweals/u-boot.git]
/
cpu
/
ppc4xx
/
kgdb.S
diff --git
a/cpu/ppc4xx/kgdb.S
b/cpu/ppc4xx/kgdb.S
index 8c4bbf2e4de35dd908e8c1b5bd94ac281005e2cf..4227a4c15b6b3b13a5fed98f6280bafdf695e1c9 100644
(file)
--- a/
cpu/ppc4xx/kgdb.S
+++ b/
cpu/ppc4xx/kgdb.S
@@
-45,7
+45,7
@@
kgdb_flush_cache_all:
iccci r0,r0 /* iccci invalidates the entire I cache */
/* dcache */
addi r6,0,0x0000 /* clear GPR 6 */
iccci r0,r0 /* iccci invalidates the entire I cache */
/* dcache */
addi r6,0,0x0000 /* clear GPR 6 */
- addi r7,r0, 128 /* do loop for # of dcache lines */
+ addi r7,r0, 128 /* do loop for # of dcache lines */
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
@@
-56,21
+56,21
@@
kgdb_flush_cache_all:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,
CFG_CACHELINE_SIZE
-1
+ li r5,
L1_CACHE_BYTES
-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,
CFG_CACHELIN
E_SHIFT
+ srwi. r4,r4,
L1_CACH
E_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,
CFG_CACHELINE_SIZE
+ addi r3,r3,
L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,
CFG_CACHELINE_SIZE
+ addi r6,r6,
L1_CACHE_BYTES
bdnz 2b
SYNC
blr
bdnz 2b
SYNC
blr