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OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000
[oweals/u-boot.git]
/
cpu
/
ppc4xx
/
denali_spd_ddr2.c
diff --git
a/cpu/ppc4xx/denali_spd_ddr2.c
b/cpu/ppc4xx/denali_spd_ddr2.c
index ad805b937b1942ed64fa7481524d225d6764c2bd..4705e21b57c0b01d64f337d688656fd52fc3420c 100644
(file)
--- a/
cpu/ppc4xx/denali_spd_ddr2.c
+++ b/
cpu/ppc4xx/denali_spd_ddr2.c
@@
-339,7
+339,7
@@
static void get_spd_info(unsigned long dimm_ranks[],
"\n", dimm_num, ranks_on_dimm);
if (ranks_on_dimm > max_ranks_per_dimm) {
printf("WARNING: DRAM DIMM in slot %lu has %lu "
"\n", dimm_num, ranks_on_dimm);
if (ranks_on_dimm > max_ranks_per_dimm) {
printf("WARNING: DRAM DIMM in slot %lu has %lu "
- "ranks.\n");
+ "ranks.\n"
, dimm_num, ranks_on_dimm
);
if (1 == max_ranks_per_dimm) {
printf("Only one rank will be used.\n");
} else {
if (1 == max_ranks_per_dimm) {
printf("Only one rank will be used.\n");
} else {
@@
-668,8
+668,8
@@
static void program_ddr0_03(unsigned long dimm_ranks[],
"and 5.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range "
"of the DIMMs.\n");
"and 5.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range "
"of the DIMMs.\n");
- printf("sdram_freq=%
d cycle2=%d cycle3=%d cycle4=%
d "
- "cycle5=%d\n\n", sdram_freq, cycle_2_0_clk,
+ printf("sdram_freq=%
ld cycle2=%ld cycle3=%ld cycle4=%l
d "
+ "cycle5=%
l
d\n\n", sdram_freq, cycle_2_0_clk,
cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang();
}
cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
spd_ddr_init_hang();
}
@@
-1022,7
+1022,7
@@
static void program_ddr0_44(unsigned long dimm_ranks[],
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-
long in
t initdram(int board_type)
+
phys_size_
t initdram(int board_type)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
@@
-1048,8
+1048,8
@@
long int initdram(int board_type)
* before continuing.
*/
/* switch to correct I2C bus */
* before continuing.
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(C
FG
_SPD_BUS_NUM);
- i2c_init(C
FG_I2C_SPEED, CFG
_I2C_SLAVE);
+ I2C_SET_BUS(C
ONFIG_SYS
_SPD_BUS_NUM);
+ i2c_init(C
ONFIG_SYS_I2C_SPEED, CONFIG_SYS
_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
@@
-1185,27
+1185,27
@@
long int initdram(int board_type)
* Map the first 1 MiB of memory in the TLB, and perform the data eye
* search.
*/
* Map the first 1 MiB of memory in the TLB, and perform the data eye
* search.
*/
- program_tlb(0, C
FG
_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
+ program_tlb(0, C
ONFIG_SYS
_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
denali_sdram_register_dump();
denali_core_search_data_eye();
denali_sdram_register_dump();
- remove_tlb(C
FG
_SDRAM_BASE, TLB_1MB_SIZE);
+ remove_tlb(C
ONFIG_SYS
_SDRAM_BASE, TLB_1MB_SIZE);
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
- program_tlb(0, C
FG
_SDRAM_BASE, dram_size, 0);
+ program_tlb(0, C
ONFIG_SYS
_SDRAM_BASE, dram_size, 0);
sync();
/* Zero the memory */
debug("Zeroing SDRAM...");
sync();
/* Zero the memory */
debug("Zeroing SDRAM...");
-#if defined(C
FG
_MEM_TOP_HIDE)
- dcbz_area(C
FG_SDRAM_BASE, dram_size - CFG
_MEM_TOP_HIDE);
+#if defined(C
ONFIG_SYS
_MEM_TOP_HIDE)
+ dcbz_area(C
ONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS
_MEM_TOP_HIDE);
#else
#else
-#error Please define C
FG
_MEM_TOP_HIDE (see README) in your board config file
+#error Please define C
ONFIG_SYS
_MEM_TOP_HIDE (see README) in your board config file
#endif
/* Write modified dcache lines back to memory */
#endif
/* Write modified dcache lines back to memory */
- clean_dcache_range(C
FG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG
_MEM_TOP_HIDE);
+ clean_dcache_range(C
ONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS
_MEM_TOP_HIDE);
debug("Completed\n");
sync();
debug("Completed\n");
sync();
- remove_tlb(C
FG
_SDRAM_BASE, dram_size);
+ remove_tlb(C
ONFIG_SYS
_SDRAM_BASE, dram_size);
#if defined(CONFIG_DDR_ECC)
/*
#if defined(CONFIG_DDR_ECC)
/*
@@
-1236,7
+1236,7
@@
long int initdram(int board_type)
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
- program_tlb(0, C
FG
_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+ program_tlb(0, C
ONFIG_SYS
_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
return dram_size;
}
return dram_size;
}
@@
-1248,7
+1248,7
@@
void board_add_ram_info(int use_default)
if (!is_ecc_enabled()) {
printf(" not");
}
if (!is_ecc_enabled()) {
printf(" not");
}
- printf(" enabled, %d MHz", (2 * get_bus_freq(0)) / 1000000);
+ printf(" enabled, %
l
d MHz", (2 * get_bus_freq(0)) / 1000000);
mfsdram(DDR0_03, val);
printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
mfsdram(DDR0_03, val);
printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);