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PPC4xx: Minimal changes to add vxWorks support
[oweals/u-boot.git]
/
cpu
/
ppc4xx
/
cpu_init.c
diff --git
a/cpu/ppc4xx/cpu_init.c
b/cpu/ppc4xx/cpu_init.c
index 66e86372603598a626166dbccc3edc91955e9ddf..01ab523c51207522e87e256cfec732febb3eb2ab 100644
(file)
--- a/
cpu/ppc4xx/cpu_init.c
+++ b/
cpu/ppc4xx/cpu_init.c
@@
-1,5
+1,5
@@
/*
/*
- * (C) Copyright 2000-200
6
+ * (C) Copyright 2000-200
7
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@
-112,7
+112,7
@@
cpu_init_f (void)
unsigned long val;
#endif
unsigned long val;
#endif
-#if
defined(CONFIG_405EP
)
+#if
(defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE
)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
/*
* GPIO0 setup (select GPIO or alternate function)
*/
@@
-128,17
+128,25
@@
cpu_init_f (void)
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+#if defined(CFG_GPIO0_ISR2H)
+ out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
+ out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+#endif
+#if defined (CFG_GPIO0_TCR)
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+#endif
+#if defined (CONFIG_450EP)
/*
* Set EMAC noise filter bits
*/
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */
/*
* Set EMAC noise filter bits
*/
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */
+#endif /* CONFIG_405EP */
-#if defined(CFG_4
40
_GPIO_TABLE)
+#if defined(CFG_4
xx
_GPIO_TABLE)
gpio_set_chip_configuration();
gpio_set_chip_configuration();
-#endif /* CFG_4
40
_GPIO_TABLE */
+#endif /* CFG_4
xx
_GPIO_TABLE */
/*
* External Bus Controller (EBC) Setup
/*
* External Bus Controller (EBC) Setup
@@
-146,14
+154,14
@@
cpu_init_f (void)
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405))
+ defined(CONFIG_405
EX) || defined(CONFIG_405
))
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
- asm volatile(" addi 4, 0, 14" ::: "r4");
+ asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
@@
-211,6
+219,8
@@
cpu_init_f (void)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
+#elif defined(CONFIG_440EPX)
+ val |= 0xb0000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif