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ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patch
[oweals/u-boot.git]
/
cpu
/
ppc4xx
/
4xx_pcie.c
diff --git
a/cpu/ppc4xx/4xx_pcie.c
b/cpu/ppc4xx/4xx_pcie.c
index f9a1988d4174c1c040819ad77545c45bb684c9ff..9803fcc768886c40e3d78ac3fb203407fe28d71c 100644
(file)
--- a/
cpu/ppc4xx/4xx_pcie.c
+++ b/
cpu/ppc4xx/4xx_pcie.c
@@
-25,11
+25,11
@@
#define DEBUG
#endif
#define DEBUG
#endif
-#include <asm/processor.h>
-#include <asm-ppc/io.h>
-#include <ppc4xx.h>
#include <common.h>
#include <pci.h>
#include <common.h>
#include <pci.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
@@
-444,8
+444,8
@@
static void ppc4xx_setup_utl(u32 port)
/*
* TODO: double check PCI express SDR based on the latest user manual
/*
* TODO: double check PCI express SDR based on the latest user manual
- * Some registers specified here no longer exist.. has to be
- * updated based on the final EAS spec.
+ * Some registers specified here no longer exist.. has to be
+ * updated based on the final EAS spec.
*/
static int check_error(void)
{
*/
static int check_error(void)
{
@@
-615,22
+615,20
@@
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
- u32 val
= 1 << 24
;
+ u32 val;
u32 utlset1;
u32 utlset1;
- if (rootport)
{
+ if (rootport)
val = PTYPE_ROOT_PORT << 20;
val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- } else {
+ else
val = PTYPE_LEGACY_ENDPOINT << 20;
val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- }
if (port == 0) {
val |= LNKW_X1 << 12;
if (port == 0) {
val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
} else {
val |= LNKW_X4 << 12;
} else {
val |= LNKW_X4 << 12;
- utlset1
|= 0x0
0101101;
+ utlset1
= 0x2
0101101;
}
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
}
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);