projects
/
oweals
/
u-boot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Merge branch 'master' of git://git.denx.de/u-boot-microblaze
[oweals/u-boot.git]
/
cpu
/
mpc8xx
/
speed.c
diff --git
a/cpu/mpc8xx/speed.c
b/cpu/mpc8xx/speed.c
index 57f91c0aa049cee3efbf5459203ea49d2eab3ae2..f309f29c0493422c2c09b73c319b1f2b2efe7729 100644
(file)
--- a/
cpu/mpc8xx/speed.c
+++ b/
cpu/mpc8xx/speed.c
@@
-27,7
+27,7
@@
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(C
FG
_MEASURE_CPUCLK) || defined(DEBUG)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(C
ONFIG_SYS
_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
#define PITC_SHIFT 16
#define PITR_SHIFT 16
@@
-87,12
+87,12
@@
static __inline__ void set_msr(unsigned long msr)
unsigned long measure_gclk(void)
{
unsigned long measure_gclk(void)
{
- volatile immap_t *immr = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immr = (immap_t *) C
ONFIG_SYS
_IMMR;
volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
ulong timer2_val;
ulong msr_val;
volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
ulong timer2_val;
ulong msr_val;
-#ifdef C
FG
_8XX_XIN
+#ifdef C
ONFIG_SYS
_8XX_XIN
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
@@
-137,7
+137,7
@@
unsigned long measure_gclk(void)
immr->im_sit.sit_pitc = SPEED_PITC_INIT;
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
immr->im_sit.sit_pitc = SPEED_PITC_INIT;
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = C
FG
_PISCR;
+ immr->im_sit.sit_piscr = C
ONFIG_SYS
_PISCR;
/*
* Start measurement - disable interrupts, just in case
/*
* Start measurement - disable interrupts, just in case
@@
-164,9
+164,9
@@
unsigned long measure_gclk(void)
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
-#if defined(C
FG
_8XX_XIN)
+#if defined(C
ONFIG_SYS
_8XX_XIN)
/* not using OSCM, using XIN, so scale appropriately */
/* not using OSCM, using XIN, so scale appropriately */
- return (((timer2_val + 2) / 4) * (C
FG
_8XX_XIN/512))/8192 * 100000L;
+ return (((timer2_val + 2) / 4) * (C
ONFIG_SYS
_8XX_XIN/512))/8192 * 100000L;
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
#endif
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
#endif
@@
-174,6
+174,27
@@
unsigned long measure_gclk(void)
#endif
#endif
+void get_brgclk(uint sccr)
+{
+ uint divider = 0;
+
+ switch((sccr&SCCR_DFBRG11)>>11){
+ case 0:
+ divider = 1;
+ break;
+ case 1:
+ divider = 4;
+ break;
+ case 2:
+ divider = 16;
+ break;
+ case 3:
+ divider = 64;
+ break;
+ }
+ gd->brg_clk = gd->cpu_clk/divider;
+}
+
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
/*
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
/*
@@
-223,6
+244,8
@@
int get_clocks (void)
gd->bus_clk = gd->cpu_clk / 2;
}
gd->bus_clk = gd->cpu_clk / 2;
}
+ get_brgclk(sccr);
+
return (0);
}
return (0);
}
@@
-238,7
+261,7
@@
static long init_pll_866 (long clk);
*/
int get_clocks_866 (void)
{
*/
int get_clocks_866 (void)
{
- volatile immap_t *immr = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immr = (immap_t *) C
ONFIG_SYS
_IMMR;
char tmp[64];
long cpuclk = 0;
long sccr_reg;
char tmp[64];
long cpuclk = 0;
long sccr_reg;
@@
-246,19
+269,22
@@
int get_clocks_866 (void)
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
- if ((C
FG_8xx_CPUCLK_MIN > cpuclk) || (CFG
_8xx_CPUCLK_MAX < cpuclk))
+ if ((C
ONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS
_8xx_CPUCLK_MAX < cpuclk))
cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
-#if defined(C
FG
_MEASURE_CPUCLK)
+#if defined(C
ONFIG_SYS
_MEASURE_CPUCLK)
gd->cpu_clk = measure_gclk ();
#endif
gd->cpu_clk = measure_gclk ();
#endif
+ get_brgclk(immr->im_clkrst.car_sccr);
+
/* if cpu clock <= 66 MHz then set bus division factor to 1,
* otherwise set it to 2
*/
sccr_reg = immr->im_clkrst.car_sccr;
sccr_reg &= ~SCCR_EBDF11;
/* if cpu clock <= 66 MHz then set bus division factor to 1,
* otherwise set it to 2
*/
sccr_reg = immr->im_clkrst.car_sccr;
sccr_reg &= ~SCCR_EBDF11;
+
if (gd->cpu_clk <= 66000000) {
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
if (gd->cpu_clk <= 66000000) {
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
gd->bus_clk = gd->cpu_clk;
@@
-275,12
+301,12
@@
int get_clocks_866 (void)
*/
int sdram_adjust_866 (void)
{
*/
int sdram_adjust_866 (void)
{
- volatile immap_t *immr = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immr = (immap_t *) C
ONFIG_SYS
_IMMR;
long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / C
FG
_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / C
ONFIG_SYS
_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
return (0);
immr->im_memctl.memc_mamr = mamr;
return (0);
@@
-294,7
+320,7
@@
static long init_pll_866 (long clk)
{
extern void plprcr_write_866 (long);
{
extern void plprcr_write_866 (long);
- volatile immap_t *immr = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immr = (immap_t *) C
ONFIG_SYS
_IMMR;
long n, plprcr;
char mfi, mfn, mfd, s, pdf;
long step_mfi, step_mfn;
long n, plprcr;
char mfi, mfn, mfd, s, pdf;
long step_mfi, step_mfn;
@@
-360,20
+386,21
@@
static long init_pll_866 (long clk)
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
/*
* Adjust sdram refresh rate to actual CPU clock
* and set timebase source according to actual CPU clock
*/
int adjust_sdram_tbs_8xx (void)
{
/*
* Adjust sdram refresh rate to actual CPU clock
* and set timebase source according to actual CPU clock
*/
int adjust_sdram_tbs_8xx (void)
{
- volatile immap_t *immr = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immr = (immap_t *) C
ONFIG_SYS
_IMMR;
long mamr;
long sccr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
long mamr;
long sccr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / C
FG
_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / C
ONFIG_SYS
_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
if (gd->cpu_clk < 67000000) {
immr->im_memctl.memc_mamr = mamr;
if (gd->cpu_clk < 67000000) {
@@
-384,6
+411,6
@@
int adjust_sdram_tbs_8xx (void)
return (0);
}
return (0);
}
-#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+#endif /* CONFIG_TQM8xxL/M, !TQM866M
, !TQM885D
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */