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Merge branch 'cleanups' into next
[oweals/u-boot.git]
/
cpu
/
mpc85xx
/
release.S
diff --git
a/cpu/mpc85xx/release.S
b/cpu/mpc85xx/release.S
index 75676b5b9e8bd9d88d2e3ce0b139cb070b29298e..54c936c3ed472c5cfea5f602c0654629c001ee1c 100644
(file)
--- a/
cpu/mpc85xx/release.S
+++ b/
cpu/mpc85xx/release.S
@@
-24,19
+24,28
@@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
+#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
ori r3,r3,HID0_TBEN@l /* enable Timebase */
+#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
+#endif
/* Enable branch prediction */
li r3,0x201
mtspr SPRN_BUCSR,r3
/* Enable branch prediction */
li r3,0x201
mtspr SPRN_BUCSR,r3
+ /* Ensure TB is 0 */
+ li r3,0
+ mttbl r3
+ mttbu r3
+
/* Enable/invalidate the I-Cache */
mfspr r0,SPRN_L1CSR1
ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
/* Enable/invalidate the I-Cache */
mfspr r0,SPRN_L1CSR1
ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
@@
-59,7
+68,11
@@
__secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+ rlwinm r4,r0,27,27,31
+#else
mr r4,r0
mr r4,r0
+#endif
slwi r8,r4,5
add r10,r3,r8
slwi r8,r4,5
add r10,r3,r8
@@
-144,6
+157,7
@@
__secondary_start_page:
mfspr r0,SPRN_PIR
stw r0,ENTRY_PIR(r10)
mfspr r0,SPRN_PIR
stw r0,ENTRY_PIR(r10)
+ mtspr IVPR,r12
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a