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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
[oweals/u-boot.git]
/
cpu
/
mpc85xx
/
cpu_init.c
diff --git
a/cpu/mpc85xx/cpu_init.c
b/cpu/mpc85xx/cpu_init.c
index 7b9961013c054a74881f43a51e79f25efd0d9697..fdb9ecbd509b47f84077cca8cd5ac8c07c0a5229 100644
(file)
--- a/
cpu/mpc85xx/cpu_init.c
+++ b/
cpu/mpc85xx/cpu_init.c
@@
-59,7
+59,7
@@
static void config_qe_ioports(void)
#endif
#ifdef CONFIG_CPM2
#endif
#ifdef CONFIG_CPM2
-
static void config_8560_ioports (volatile immap_t * immr
)
+
void config_8560_ioports (volatile ccsr_cpm_t * cpm
)
{
int portnum;
{
int portnum;
@@
-99,7
+99,7
@@
static void config_8560_ioports (volatile immap_t * immr)
}
if (pmsk != 0) {
}
if (pmsk != 0) {
- volatile ioport_t *iop = ioport_addr (
immr
, portnum);
+ volatile ioport_t *iop = ioport_addr (
cpm
, portnum);
uint tpmsk = ~pmsk;
/*
uint tpmsk = ~pmsk;
/*
@@
-131,8
+131,7
@@
static void config_8560_ioports (volatile immap_t * immr)
void cpu_init_f (void)
{
void cpu_init_f (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
extern void m8560_cpm_reset (void);
/* Pointer is writable since we allocated a register for it */
@@
-143,7
+142,7
@@
void cpu_init_f (void)
#ifdef CONFIG_CPM2
#ifdef CONFIG_CPM2
- config_8560_ioports(
immap
);
+ config_8560_ioports(
(ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR
);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@
-222,18
+221,15
@@
void cpu_init_f (void)
int cpu_init_r(void)
{
int cpu_init_r(void)
{
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#endif
#ifdef CONFIG_CLEAR_LAW0
#ifdef CONFIG_CLEAR_LAW0
- volatile ccsr_local_ecm_t *ecm =
&immap->im_local_ecm
;
+ volatile ccsr_local_ecm_t *ecm =
(void *)(CFG_MPC85xx_ECM_ADDR)
;
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache =
&immap->im_l2cache
;
+ volatile ccsr_l2cache_t *l2cache =
(void *)CFG_MPC85xx_L2_ADDR
;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
@@
-247,7
+243,7
@@
int cpu_init_r(void)
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
- ver == SVR_8544) {
+ ver == SVR_8544
|| ver == SVR_8568_E
) {
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;