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Add a unified s3c24x0 header file
[oweals/u-boot.git]
/
cpu
/
mpc512x
/
cpu_init.c
diff --git
a/cpu/mpc512x/cpu_init.c
b/cpu/mpc512x/cpu_init.c
index fa753c8e70e2632888b8906c637f130893b7355c..fe6beaf84d28843edf9043a2b088b63af29c3557 100644
(file)
--- a/
cpu/mpc512x/cpu_init.c
+++ b/
cpu/mpc512x/cpu_init.c
@@
-1,6
+1,6
@@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- *
(C) Copyright 2007
DENX Software Engineering
+ *
Copyright (C) 2007-2009
DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* See file CREDITS for list of people who contributed to this
* project.
@@
-25,7
+25,8
@@
*/
#include <common.h>
*/
#include <common.h>
-#include <mpc512x.h>
+#include <asm/io.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
@@
-46,30
+47,34
@@
void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ out_be32(&im->arbiter.acr,
+ (im->arbiter.acr & ~ACR_PIPE_DEP) |
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+ );
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
- im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+ out_be32(im->arbiter.acr,
+ (im->arbiter.acr & ~(ACR_RPTCNT)) |
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+ );
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
-
im->reset.rsr = ~(
RSR_RES);
+
out_be32(&im->reset.rsr, ~
RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
-
im->reset.rmr = (
RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+
out_be32(&im->reset.rmr,
RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
/* Set IPS-CSB divider: IPS = 1/2 CSB */
- ips_div = i
m->clk.scfr[0]
;
+ ips_div = i
n_be32(&im->clk.scfr[0])
;
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
-
im->clk.scfr[0] = ips_div
;
+
out_be32(&im->clk.scfr[0], ips_div)
;
/*
* Enable Time Base/Decrementer
/*
* Enable Time Base/Decrementer
@@
-78,7
+83,7
@@
void cpu_init_f (volatile immap_t * im)
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
-
im->sysconf.spcr |= SPCR_TBEN
;
+
setbits_be32(&im->sysconf.spcr, SPCR_TBEN)
;
}
int cpu_init_r (void)
}
int cpu_init_r (void)