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cpu/ppc4xx/fdt.c: avoid strcpy() to constant string
[oweals/u-boot.git]
/
cpu
/
mcf52x2
/
speed.c
diff --git
a/cpu/mcf52x2/speed.c
b/cpu/mcf52x2/speed.c
index 4cb8f9300d9c8e97435e052cc7762781b9036deb..b485e1cccc129516c50acb3080bd1ec006f04762 100644
(file)
--- a/
cpu/mcf52x2/speed.c
+++ b/
cpu/mcf52x2/speed.c
@@
-30,20
+30,25
@@
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks (void)
{
int get_clocks (void)
{
+#if defined(CONFIG_M5208)
+ volatile pll_t *pll = (pll_t *) MMAP_PLL;
+
+ pll->odr = CONFIG_SYS_PLL_ODR;
+ pll->fdr = CONFIG_SYS_PLL_FDR;
+#endif
+
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef C
FG
_PLL_BYPASS
+#ifndef C
ONFIG_SYS
_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef C
FG
_FAST_CLK
+#ifdef C
ONFIG_SYS
_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@
-51,7
+56,7
@@
int get_clocks (void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = C
FG
_PLLCR;
+ pllcr = C
ONFIG_SYS
_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@
-60,7
+65,7
@@
int get_clocks (void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef C
FG
_PLL_BYPASS */
+#endif /* #ifndef C
ONFIG_SYS
_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@
-76,8
+81,9
@@
int get_clocks (void)
;
#endif
;
#endif
- gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+ gd->cpu_clk = CONFIG_SYS_CLK;
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+ defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
@@
-85,7
+91,7
@@
int get_clocks (void)
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
-#ifdef C
FG
_I2C2_OFFSET
+#ifdef C
ONFIG_SYS
_I2C2_OFFSET
gd->i2c2_clk = gd->bus_clk;
#endif
#endif
gd->i2c2_clk = gd->bus_clk;
#endif
#endif