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Blackfin: split cpu COBJS into multilines
[oweals/u-boot.git]
/
cpu
/
blackfin
/
reset.c
diff --git
a/cpu/blackfin/reset.c
b/cpu/blackfin/reset.c
index d1e34b3f94ce9d849c4300c02295cbb99bcc8164..e3be7407115a4d3de43a3d39ae7937db476944b9 100644
(file)
--- a/
cpu/blackfin/reset.c
+++ b/
cpu/blackfin/reset.c
@@
-20,7
+20,7
@@
* the core reset.
*/
__attribute__ ((__l1_text__, __noreturn__))
* the core reset.
*/
__attribute__ ((__l1_text__, __noreturn__))
-void bfin_reset(void)
+
static
void bfin_reset(void)
{
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
{
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
@@
-29,26
+29,35
@@
void bfin_reset(void)
*/
__builtin_bfin_ssync();
*/
__builtin_bfin_ssync();
- while (1) {
+ /* The bootrom checks to see how it was reset and will
+ * automatically perform a software reset for us when
+ * it starts executing after the core reset.
+ */
+ if (ANOMALY_05000353 || ANOMALY_05000386) {
/* Initiate System software reset. */
bfin_write_SWRST(0x7);
/* Due to the way reset is handled in the hardware, we need
/* Initiate System software reset. */
bfin_write_SWRST(0x7);
/* Due to the way reset is handled in the hardware, we need
- * to delay for
7
SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply
7
. For now,
+ * to delay for
10
SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply
10
. For now,
* we'll assume worse case which is a 1:15 ratio.
*/
asm(
"LSETUP (1f, 1f) LC0 = %0\n"
"1: nop;"
:
* we'll assume worse case which is a 1:15 ratio.
*/
asm(
"LSETUP (1f, 1f) LC0 = %0\n"
"1: nop;"
:
- : "a" (15 *
7
)
+ : "a" (15 *
10
)
: "LC0", "LB0", "LT0"
);
/* Clear System software reset */
bfin_write_SWRST(0);
: "LC0", "LB0", "LT0"
);
/* Clear System software reset */
bfin_write_SWRST(0);
+ /* The BF526 ROM will crash during reset */
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+ bfin_read_SWRST();
+#endif
+
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
* though as the System state is all reset now.
*/
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
* though as the System state is all reset now.
*/
@@
-59,10
+68,11
@@
void bfin_reset(void)
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
+ }
+ while (1)
/* Issue core reset */
asm("raise 1");
/* Issue core reset */
asm("raise 1");
- }
}
/* We need to trampoline ourselves up into L1 since our linker
}
/* We need to trampoline ourselves up into L1 since our linker