+#elif defined(CONFIG_NETARM)
+ /*
+ * prior to software reset : need to set pin PORTC4 to be *HRESET
+ */
+ ldr r0, =NETARM_GEN_MODULE_BASE
+ ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
+ NETARM_GEN_PORT_DIR(0x10))
+ str r1, [r0, #+NETARM_GEN_PORTC]
+ /*
+ * software reset : see HW Ref. Guide 8.2.4 : Software Service register
+ * for an explanation of this process
+ */
+ ldr r0, =NETARM_GEN_MODULE_BASE
+ ldr r1, =NETARM_GEN_SW_SVC_RESETA
+ str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+ ldr r1, =NETARM_GEN_SW_SVC_RESETB
+ str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+ ldr r1, =NETARM_GEN_SW_SVC_RESETA
+ str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+ ldr r1, =NETARM_GEN_SW_SVC_RESETB
+ str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+ /*
+ * setup PLL and System Config
+ */
+ ldr r0, =NETARM_GEN_MODULE_BASE
+
+ ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
+ NETARM_GEN_SYS_CFG_BUSFULL | \
+ NETARM_GEN_SYS_CFG_USER_EN | \
+ NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
+ NETARM_GEN_SYS_CFG_BUSARB_INT | \
+ NETARM_GEN_SYS_CFG_BUSMON_EN )
+
+ str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
+
+ ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
+ NETARM_GEN_PLL_CTL_POLTST_DEF | \
+ NETARM_GEN_PLL_CTL_INDIV(1) | \
+ NETARM_GEN_PLL_CTL_ICP_DEF | \
+ NETARM_GEN_PLL_CTL_OUTDIV(2) )
+ str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
+ /*
+ * mask all IRQs by clearing all bits in the INTMRs
+ */
+ mov r1, #0
+ ldr r0, =NETARM_GEN_MODULE_BASE
+ str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
+
+#elif defined(CONFIG_S3C4510B)
+
+ /*
+ * Mask off all IRQ sources
+ */
+ ldr r1, =REG_INTMASK
+ ldr r0, =0x3FFFFF
+ str r0, [r1]
+
+ /*
+ * Disable Cache
+ */
+ ldr r0, =REG_SYSCFG
+ ldr r1, =0x83ffffa0 /* cache-disabled */
+ str r1, [r0]
+
+#else
+#error No cpu_init_crit() defined for current CPU type
+#endif