- printf("Number of banks %d\n", data[17]);
- puts ("CAS latency(s) ");
- if (data[18] & 0x80) puts (" TBD");
- if (data[18] & 0x40) puts (" 7");
- if (data[18] & 0x20) puts (" 6");
- if (data[18] & 0x10) puts (" 5");
- if (data[18] & 0x08) puts (" 4");
- if (data[18] & 0x04) puts (" 3");
- if (data[18] & 0x02) puts (" 2");
- if (data[18] & 0x01) puts (" 1");
- putc ('\n');
- puts ("CS latency(s) ");
- if (data[19] & 0x80) puts (" TBD");
- if (data[19] & 0x40) puts (" 6");
- if (data[19] & 0x20) puts (" 5");
- if (data[19] & 0x10) puts (" 4");
- if (data[19] & 0x08) puts (" 3");
- if (data[19] & 0x04) puts (" 2");
- if (data[19] & 0x02) puts (" 1");
- if (data[19] & 0x01) puts (" 0");
- putc ('\n');
- puts ("WE latency(s) ");
- if (data[20] & 0x80) puts (" TBD");
- if (data[20] & 0x40) puts (" 6");
- if (data[20] & 0x20) puts (" 5");
- if (data[20] & 0x10) puts (" 4");
- if (data[20] & 0x08) puts (" 3");
- if (data[20] & 0x04) puts (" 2");
- if (data[20] & 0x02) puts (" 1");
- if (data[20] & 0x01) puts (" 0");
- putc ('\n');
- puts ("Module attributes:\n");
- if (!data[21]) puts (" (none)\n");
- if (data[21] & 0x80) puts (" TBD (bit 7)\n");
- if (data[21] & 0x40) puts (" Redundant row address\n");
- if (data[21] & 0x20) puts (" Differential clock input\n");
- if (data[21] & 0x10) puts (" Registerd DQMB inputs\n");
- if (data[21] & 0x08) puts (" Buffered DQMB inputs\n");
- if (data[21] & 0x04) puts (" On-card PLL\n");
- if (data[21] & 0x02) puts (" Registered address/control lines\n");
- if (data[21] & 0x01) puts (" Buffered address/control lines\n");
- puts ("Device attributes:\n");
- if (data[22] & 0x80) puts (" TBD (bit 7)\n");
- if (data[22] & 0x40) puts (" TBD (bit 6)\n");
- if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
- else puts (" Upper Vcc tolerance 10%\n");
- if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
- else puts (" Lower Vcc tolerance 10%\n");
- if (data[22] & 0x08) puts (" Supports write1/read burst\n");
- if (data[22] & 0x04) puts (" Supports precharge all\n");
- if (data[22] & 0x02) puts (" Supports auto precharge\n");
- if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
- printf("SDRAM cycle time (2nd highest CAS latency) %d.%d nS\n",
- (data[23] >> 4) & 0x0F, data[23] & 0x0F);
- printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n",
- (data[24] >> 4) & 0x0F, data[24] & 0x0F);
- printf("SDRAM cycle time (3rd highest CAS latency) %d.%d nS\n",
- (data[25] >> 4) & 0x0F, data[25] & 0x0F);
- printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n",
- (data[26] >> 4) & 0x0F, data[26] & 0x0F);
- printf("Minimum row precharge %d nS\n", data[27]);
- printf("Row active to row active min %d nS\n", data[28]);
- printf("RAS to CAS delay min %d nS\n", data[29]);
- printf("Minimum RAS pulse width %d nS\n", data[30]);
- puts ("Density of each row ");
- if (data[31] & 0x80) puts (" 512");
- if (data[31] & 0x40) puts (" 256");
- if (data[31] & 0x20) puts (" 128");
- if (data[31] & 0x10) puts (" 64");
- if (data[31] & 0x08) puts (" 32");
- if (data[31] & 0x04) puts (" 16");
- if (data[31] & 0x02) puts (" 8");
- if (data[31] & 0x01) puts (" 4");
- puts ("MByte\n");
- printf("Command and Address setup %c%d.%d nS\n",
- (data[32] & 0x80) ? '-' : '+',
- (data[32] >> 4) & 0x07, data[32] & 0x0F);
- printf("Command and Address hold %c%d.%d nS\n",
- (data[33] & 0x80) ? '-' : '+',
- (data[33] >> 4) & 0x07, data[33] & 0x0F);
- printf("Data signal input setup %c%d.%d nS\n",
- (data[34] & 0x80) ? '-' : '+',
- (data[34] >> 4) & 0x07, data[34] & 0x0F);
- printf("Data signal input hold %c%d.%d nS\n",
- (data[35] & 0x80) ? '-' : '+',
- (data[35] >> 4) & 0x07, data[35] & 0x0F);
+ printf ("Number of banks %d\n", data[17]);
+
+ switch (type) {
+ case DDR2:
+ puts ("CAS latency(s) ");
+ decode_bits (data[18], decode_CAS_DDR2, 0);
+ putc ('\n');
+ break;
+ default:
+ puts ("CAS latency(s) ");
+ decode_bits (data[18], decode_CAS_default, 0);
+ putc ('\n');
+ break;
+ }
+
+ if (DDR2 != type) {
+ puts ("CS latency(s) ");
+ decode_bits (data[19], decode_CS_WE_default, 0);
+ putc ('\n');
+ }
+
+ if (DDR2 != type) {
+ puts ("WE latency(s) ");
+ decode_bits (data[20], decode_CS_WE_default, 0);
+ putc ('\n');
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Module attributes:\n");
+ if (data[21] & 0x80)
+ puts (" TBD (bit 7)\n");
+ if (data[21] & 0x40)
+ puts (" Analysis probe installed\n");
+ if (data[21] & 0x20)
+ puts (" TBD (bit 5)\n");
+ if (data[21] & 0x10)
+ puts (" FET switch external enable\n");
+ printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
+ if (data[20] & 0x11) {
+ printf (" %d active registers on DIMM\n",
+ (data[21] & 0x03) + 1);
+ }
+ break;
+ default:
+ puts ("Module attributes:\n");
+ if (!data[21])
+ puts (" (none)\n");
+ else
+ decode_bits (data[21], decode_byte21_default, 0);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ decode_bits (data[22], decode_byte22_DDR2, 0);
+ break;
+ default:
+ puts ("Device attributes:\n");
+ if (data[22] & 0x80) puts (" TBD (bit 7)\n");
+ if (data[22] & 0x40) puts (" TBD (bit 6)\n");
+ if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
+ else puts (" Upper Vcc tolerance 10%\n");
+ if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
+ else puts (" Lower Vcc tolerance 10%\n");
+ if (data[22] & 0x08) puts (" Supports write1/read burst\n");
+ if (data[22] & 0x04) puts (" Supports precharge all\n");
+ if (data[22] & 0x02) puts (" Supports auto precharge\n");
+ if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM cycle time (2nd highest CAS latency) ");
+ print_ddr2_tcyc (data[23]);
+ break;
+ default:
+ printf ("SDRAM cycle time (2nd highest CAS latency) %d."
+ "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM access from clock (2nd highest CAS latency) 0."
+ "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+ break;
+ default:
+ printf ("SDRAM access from clock (2nd highest CAS latency) %d."
+ "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM cycle time (3rd highest CAS latency) ");
+ print_ddr2_tcyc (data[25]);
+ break;
+ default:
+ printf ("SDRAM cycle time (3rd highest CAS latency) %d."
+ "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM access from clock (3rd highest CAS latency) 0."
+ "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+ break;
+ default:
+ printf ("SDRAM access from clock (3rd highest CAS latency) %d."
+ "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Minimum row precharge %d.%02d ns\n",
+ (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
+ break;
+ default:
+ printf ("Minimum row precharge %d ns\n", data[27]);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Row active to row active min %d.%02d ns\n",
+ (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
+ break;
+ default:
+ printf ("Row active to row active min %d ns\n", data[28]);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("RAS to CAS delay min %d.%02d ns\n",
+ (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
+ break;
+ default:
+ printf ("RAS to CAS delay min %d ns\n", data[29]);
+ break;
+ }
+
+ printf ("Minimum RAS pulse width %d ns\n", data[30]);
+
+ switch (type) {
+ case DDR2:
+ puts ("Density of each row ");
+ decode_bits (data[31], decode_row_density_DDR2, 1);
+ putc ('\n');
+ break;
+ default:
+ puts ("Density of each row ");
+ decode_bits (data[31], decode_row_density_default, 1);
+ putc ('\n');
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Command and Address setup ");
+ if (data[32] >= 0xA0) {
+ printf ("1.%d%d ns\n",
+ ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
+ } else {
+ printf ("0.%d%d ns\n",
+ ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
+ }
+ break;
+ default:
+ printf ("Command and Address setup %c%d.%d ns\n",
+ (data[32] & 0x80) ? '-' : '+',
+ (data[32] >> 4) & 0x07, data[32] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Command and Address hold ");
+ if (data[33] >= 0xA0) {
+ printf ("1.%d%d ns\n",
+ ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
+ } else {
+ printf ("0.%d%d ns\n",
+ ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
+ }
+ break;
+ default:
+ printf ("Command and Address hold %c%d.%d ns\n",
+ (data[33] & 0x80) ? '-' : '+',
+ (data[33] >> 4) & 0x07, data[33] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Data signal input setup 0.%d%d ns\n",
+ (data[34] >> 4) & 0x0F, data[34] & 0x0F);
+ break;
+ default:
+ printf ("Data signal input setup %c%d.%d ns\n",
+ (data[34] & 0x80) ? '-' : '+',
+ (data[34] >> 4) & 0x07, data[34] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Data signal input hold 0.%d%d ns\n",
+ (data[35] >> 4) & 0x0F, data[35] & 0x0F);
+ break;
+ default:
+ printf ("Data signal input hold %c%d.%d ns\n",
+ (data[35] & 0x80) ? '-' : '+',
+ (data[35] >> 4) & 0x07, data[35] & 0x0F);
+ break;
+ }
+