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Merge git://www.denx.de/git/u-boot
[oweals/u-boot.git]
/
board
/
xilinx
/
ml401
/
xparameters.h
diff --git
a/board/xilinx/ml401/xparameters.h
b/board/xilinx/ml401/xparameters.h
index 18d24f9c1d1ed07d195531dc133f800db6d023f4..1a116ead1b78c211e93c5f3fd8d7e00508f82885 100644
(file)
--- a/
board/xilinx/ml401/xparameters.h
+++ b/
board/xilinx/ml401/xparameters.h
@@
-21,47
+21,55
@@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- *
* CAUTION: This file is automatically generated by libgen.
* CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK
6.3 EDK_Gmm.12.3
+ * Version: Xilinx EDK
8.2.02 EDK_Im_Sp2.4
*/
/* System Clock Frequency */
*/
/* System Clock Frequency */
-#define XILINX_CLOCK_FREQ 66666667
+#define XILINX_CLOCK_FREQ 100000000
+
+/* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR 1
+#define XILINX_FSL_NUMBER 3
-/* Interrupt controller is intc_0 */
-#define XILINX_INTC_BASEADDR 0x
d1000fc
0
-#define XILINX_INTC_NUM_INTR_INPUTS
12
+/* Interrupt controller is
opb_
intc_0 */
+#define XILINX_INTC_BASEADDR 0x
4120000
0
+#define XILINX_INTC_NUM_INTR_INPUTS
6
-/* Timer pheriphery is opb_timer_
0
*/
-#define XILINX_TIMER_BASEADDR 0x
a20
00000
+/* Timer pheriphery is opb_timer_
1
*/
+#define XILINX_TIMER_BASEADDR 0x
41c
00000
#define XILINX_TIMER_IRQ 0
#define XILINX_TIMER_IRQ 0
-/* Uart pheriphery is
console_u
art */
-#define XILINX_UART_BASEADDR 0x
a00
00000
+/* Uart pheriphery is
RS232_U
art */
+#define XILINX_UART_BASEADDR 0x
406
00000
#define XILINX_UART_BAUDRATE 115200
#define XILINX_UART_BAUDRATE 115200
-/* GPIO is opb_gpio_0*/
-#define XILINX_GPIO_BASEADDR 0x90000000
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR 0x40800000
+#define XILINX_IIC_0_FREQ 100000
+#define XILINX_IIC_0_BIT 0
+
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR 0x40000000
-/* Flash Memory is
opb_emc_0
*/
-#define XILINX_FLASH_START 0x2
8
000000
+/* Flash Memory is
FLASH_2Mx32
*/
+#define XILINX_FLASH_START 0x2
c
000000
#define XILINX_FLASH_SIZE 0x00800000
#define XILINX_FLASH_SIZE 0x00800000
-/* Main Memory is
plb_ddr_0
*/
-#define XILINX_RAM_START 0x
10
000000
-#define XILINX_RAM_SIZE 0x
10
000000
+/* Main Memory is
DDR_SDRAM_64Mx32
*/
+#define XILINX_RAM_START 0x
28
000000
+#define XILINX_RAM_SIZE 0x
04
000000
-/* Sysace Controller is
opb_sysace_0
*/
-#define XILINX_SYSACE_BASEADDR 0x
CF0
00000
-#define XILINX_SYSACE_HIGHADDR 0x
CF0001FF
+/* Sysace Controller is
SysACE_CompactFlash
*/
+#define XILINX_SYSACE_BASEADDR 0x
418
00000
+#define XILINX_SYSACE_HIGHADDR 0x
4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
#define XILINX_SYSACE_MEM_WIDTH 16
-/* Ethernet controller is
opb_ethernet_0
*/
+/* Ethernet controller is
Ethernet_MAC
*/
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x
600
00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x
60003FFF
+#define XPAR_OPB_ETHERNET_0_BASEADDR 0x
40c
00000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x
40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1