- at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
- at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
- at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
- at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
- at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
- at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
- at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
- at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
- at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
- at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
- at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
- at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
- at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
- at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
- at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
- at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
- at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
- at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
- at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
- at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
- at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
-
- at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
+ at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
+ at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
+ at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
+ at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
+ at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
+
+ writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */