-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OVERO;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: get_board_revision
- * Description: Returns the board revision
- */
-int get_board_revision(void)
-{
- int revision;
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- unsigned char data;
-
- /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
- /* these boards should return a revision number of 0 */
- /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
- i2c_set_bus_num(TWL4030_I2C_BUS);
- data = 0x01;
- i2c_write(0x4B, 0x29, 1, &data, 1);
- data = 0x0c;
- i2c_write(0x4B, 0x2b, 1, &data, 1);
- i2c_read(0x4B, 0x2a, 1, &data, 1);
-#endif
-
- if (!gpio_request(112, "") &&
- !gpio_request(113, "") &&
- !gpio_request(115, "")) {
-
- gpio_direction_input(112);
- gpio_direction_input(113);
- gpio_direction_input(115);
-
- revision = gpio_get_value(115) << 2 |
- gpio_get_value(113) << 1 |
- gpio_get_value(112);
- } else {
- puts("Error: unable to acquire board revision GPIOs\n");
- revision = -1;
- }
-
- return revision;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mr = MICRON_V_MR_165;
- switch (get_board_revision()) {
- case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- timings->mcfg = MICRON_V_MCFG_165(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_165;
- timings->ctrlb = HYNIX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- default:
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
-}
-#endif