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Add bootcount to AT91
[oweals/u-boot.git]
/
board
/
mx1fs2
/
lowlevel_init.S
diff --git
a/board/mx1fs2/lowlevel_init.S
b/board/mx1fs2/lowlevel_init.S
index 4b2cb487aadb0ead6ec196e76b444f2eb9528581..56a4819b0891478e0699dd32df04dd69c0fd63e7 100644
(file)
--- a/
board/mx1fs2/lowlevel_init.S
+++ b/
board/mx1fs2/lowlevel_init.S
@@
-29,19
+29,19
@@
lowlevel_init:
/* Change PERCLK1DIV to 14 ie 14+1 */
ldr r0, =PCDR
/* Change PERCLK1DIV to 14 ie 14+1 */
ldr r0, =PCDR
- ldr r1, =C
FG
_PCDR_VAL
+ ldr r1, =C
ONFIG_SYS
_PCDR_VAL
str r1, [r0]
/* set MCU PLL Control Register 0 */
ldr r0, =MPCTL0
str r1, [r0]
/* set MCU PLL Control Register 0 */
ldr r0, =MPCTL0
- ldr r1, =C
FG
_MPCTL0_VAL
+ ldr r1, =C
ONFIG_SYS
_MPCTL0_VAL
str r1, [r0]
/* set MCU PLL Control Register 1 */
ldr r0, =MPCTL1
str r1, [r0]
/* set MCU PLL Control Register 1 */
ldr r0, =MPCTL1
- ldr r1, =C
FG
_MPCTL1_VAL
+ ldr r1, =C
ONFIG_SYS
_MPCTL1_VAL
str r1, [r0]
/* set mpll restart bit */
str r1, [r0]
/* set mpll restart bit */
@@
-63,13
+63,13
@@
lowlevel_init:
/* set System PLL Control Register 0 */
ldr r0, =SPCTL0
/* set System PLL Control Register 0 */
ldr r0, =SPCTL0
- ldr r1, =C
FG
_SPCTL0_VAL
+ ldr r1, =C
ONFIG_SYS
_SPCTL0_VAL
str r1, [r0]
/* set System PLL Control Register 1 */
ldr r0, =SPCTL1
str r1, [r0]
/* set System PLL Control Register 1 */
ldr r0, =SPCTL1
- ldr r1, =C
FG
_SPCTL1_VAL
+ ldr r1, =C
ONFIG_SYS
_SPCTL1_VAL
str r1, [r0]
/* set spll restart bit */
str r1, [r0]
/* set spll restart bit */
@@
-89,11
+89,11
@@
lowlevel_init:
bne 1b
ldr r0, =CSCR
bne 1b
ldr r0, =CSCR
- ldr r1, =C
FG
_CSCR_VAL
+ ldr r1, =C
ONFIG_SYS
_CSCR_VAL
str r1, [r0]
ldr r0, =GPCR
str r1, [r0]
ldr r0, =GPCR
- ldr r1, =C
FG
_GPCR_VAL
+ ldr r1, =C
ONFIG_SYS
_GPCR_VAL
str r1, [r0]
/*
str r1, [r0]
/*
@@
-122,43
+122,43
@@
lowlevel_init:
MCR p15,0,r0,c1,c0,0
ldr r0, =GIUS(0)
MCR p15,0,r0,c1,c0,0
ldr r0, =GIUS(0)
- ldr r1, =C
FG
_GIUS_A_VAL
+ ldr r1, =C
ONFIG_SYS
_GIUS_A_VAL
str r1, [r0]
ldr r0, =FMCR
str r1, [r0]
ldr r0, =FMCR
- ldr r1, =C
FG
_FMCR_VAL
+ ldr r1, =C
ONFIG_SYS
_FMCR_VAL
str r1, [r0]
ldr r0, =CS0U
str r1, [r0]
ldr r0, =CS0U
- ldr r1, =C
FG
_CS0U_VAL
+ ldr r1, =C
ONFIG_SYS
_CS0U_VAL
str r1, [r0]
ldr r0, =CS0L
str r1, [r0]
ldr r0, =CS0L
- ldr r1, =C
FG
_CS0L_VAL
+ ldr r1, =C
ONFIG_SYS
_CS0L_VAL
str r1, [r0]
ldr r0, =CS1U
str r1, [r0]
ldr r0, =CS1U
- ldr r1, =C
FG
_CS1U_VAL
+ ldr r1, =C
ONFIG_SYS
_CS1U_VAL
str r1, [r0]
ldr r0, =CS1L
str r1, [r0]
ldr r0, =CS1L
- ldr r1, =C
FG
_CS1L_VAL
+ ldr r1, =C
ONFIG_SYS
_CS1L_VAL
str r1, [r0]
ldr r0, =CS4U
str r1, [r0]
ldr r0, =CS4U
- ldr r1, =C
FG
_CS4U_VAL
+ ldr r1, =C
ONFIG_SYS
_CS4U_VAL
str r1, [r0]
ldr r0, =CS4L
str r1, [r0]
ldr r0, =CS4L
- ldr r1, =C
FG
_CS4L_VAL
+ ldr r1, =C
ONFIG_SYS
_CS4L_VAL
str r1, [r0]
ldr r0, =CS5U
str r1, [r0]
ldr r0, =CS5U
- ldr r1, =C
FG
_CS5U_VAL
+ ldr r1, =C
ONFIG_SYS
_CS5U_VAL
str r1, [r0]
ldr r0, =CS5L
str r1, [r0]
ldr r0, =CS5L
- ldr r1, =C
FG
_CS5L_VAL
+ ldr r1, =C
ONFIG_SYS
_CS5L_VAL
str r1, [r0]
/* SDRAM Setup */
str r1, [r0]
/* SDRAM Setup */