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sf: stmicro: Add support for N25Q512
[oweals/u-boot.git]
/
board
/
mx1ads
/
mx1ads.c
diff --git
a/board/mx1ads/mx1ads.c
b/board/mx1ads/mx1ads.c
index 913f95c5e89180e97f4c2f23512335a200aa4a6c..da9e21dddbb7bc64f38c33dcafa3c2ef256b0b5f 100644
(file)
--- a/
board/mx1ads/mx1ads.c
+++ b/
board/mx1ads/mx1ads.c
@@
-24,8
+24,10
@@
*/
#include <common.h>
*/
#include <common.h>
+#include <netdev.h>
/*#include <mc9328.h>*/
#include <asm/arch/imx-regs.h>
/*#include <mc9328.h>*/
#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
@@
-77,16
+79,14
@@
void SetAsynchMode (void)
static u32 mc9328sid;
static u32 mc9328sid;
-int board_
init
(void)
+int board_
early_init_f
(void)
{
{
- volatile unsigned int tmp;
-
mc9328sid = SIDR;
GPCR = 0x000003AB; /* I/O pad driving strength */
mc9328sid = SIDR;
GPCR = 0x000003AB; /* I/O pad driving strength */
- /* MX1_CS1U = 0x00000A00; *//* SRAM initialization */
-/* MX1_CS1L = 0x11110601; */
+ /* MX1_CS1U = 0x00000A00; */
/* SRAM initialization */
+/* MX1_CS1L = 0x11110601; */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
@@
-106,15
+106,11
@@
int board_init (void)
GIUS (0) &= 0xFF3FFFFF;
GPR (0) &= 0xFF3FFFFF;
GIUS (0) &= 0xFF3FFFFF;
GPR (0) &= 0xFF3FFFFF;
-
tmp = *(unsigned int *)
(0x1500000C);
-
tmp = *(unsigned int *)
(0x1500000C);
+
readl
(0x1500000C);
+
readl
(0x1500000C);
SetAsynchMode ();
SetAsynchMode ();
- gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
-
- gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
-
icache_enable ();
dcache_enable ();
icache_enable ();
dcache_enable ();
@@
-132,6
+128,15
@@
int board_init (void)
return 0;
}
return 0;
}
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
+
+ gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
+
+ return 0;
+}
+
int board_late_init (void)
{
int board_late_init (void)
{
@@
-160,10
+165,27
@@
int board_late_init (void)
return 0;
}
return 0;
}
-int dram_init (void)
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
- return 0;
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
}
}
+#endif