-#define B1_BWSCON (DW16)
-#define B2_BWSCON (DW32)
-#define B3_BWSCON (DW32)
-#define B4_BWSCON (DW16 + WAIT + UBLB)
-#define B5_BWSCON (DW8 + UBLB)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x1 /* 1clk */
-/*#define B0_Tcos 0x0 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-/*#define B0_Tacc 0x5 8clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0 /* page mode is not used */
-#define B0_PMC 0x0 /* page mode disabled */
-
-/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x1 /* 1clk */
-/*#define B1_Tcos 0x0 0clk */
-#define B1_Tacc 0x7 /* 14clk */
-/*#define B1_Tacc 0x5 8clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0 /* page mode is not used */
-#define B1_PMC 0x0 /* page mode disabled */
-
-#define B2_Tacs 0x3 /* 4clk */
-#define B2_Tcos 0x3 /* 4clk */
-#define B2_Tacc 0x7 /* 14clk */
-#define B2_Tcoh 0x3 /* 4clk */
-#define B2_Tah 0x3 /* 4clk */
-#define B2_Tacp 0x0 /* page mode is not used */
-#define B2_PMC 0x0 /* page mode disabled */
-
-#define B3_Tacs 0x3 /* 4clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x3 /* 4clk */
-#define B3_Tah 0x3 /* 4clk */
-#define B3_Tacp 0x0 /* page mode is not used */
-#define B3_PMC 0x0 /* page mode disabled */
-
-#define B4_Tacs 0x3 /* 4clk */
-#define B4_Tcos 0x1 /* 1clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x1 /* 1clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0 /* page mode is not used */
-#define B4_PMC 0x0 /* page mode disabled */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x3 /* 4clk */
-#define B5_Tacc 0x5 /* 8clk */
-#define B5_Tcoh 0x2 /* 2clk */
-#define B5_Tah 0x1 /* 1clk */
-#define B5_Tacp 0x0 /* page mode is not used */
-#define B5_PMC 0x0 /* page mode disabled */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1 /* 3clk */
-#define B6_SCAN 0x2 /* 10bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x2 /* 10bit */
+/* BANK0CON 200 */
+#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
+#define B0_Tcoh_200 0x0 /* 0clk */
+#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
+#define B0_Tacp_200 0x0 /* page mode is not used */
+#define B0_PMC_200 0x0 /* page mode disabled */
+
+/* BANK0CON 250 */
+#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
+#define B0_Tcoh_250 0x0 /* 0clk */
+#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
+#define B0_Tacp_250 0x0 /* page mode is not used */
+#define B0_PMC_250 0x0 /* page mode disabled */
+
+/* BANK0CON 266 */
+#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
+#define B0_Tcoh_266 0x0 /* 0clk */
+#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
+#define B0_Tacp_266 0x0 /* page mode is not used */
+#define B0_PMC_266 0x0 /* page mode disabled */
+
+/* BANK1CON 200 */
+#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
+#define B1_Tcoh_200 0x0 /* 0clk */
+#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_200 0x0 /* page mode is not used */
+#define B1_PMC_200 0x0 /* page mode disabled */
+
+/* BANK1CON 250 */
+#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
+#define B1_Tcoh_250 0x0 /* 0clk */
+#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_250 0x0 /* page mode is not used */
+#define B1_PMC_250 0x0 /* page mode disabled */
+
+/* BANK1CON 266 */
+#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
+#define B1_Tcoh_266 0x0 /* 0clk */
+#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_266 0x0 /* page mode is not used */
+#define B1_PMC_266 0x0 /* page mode disabled */
+
+/* BANK2CON 200 + 250 + 266 */
+#define B2_Tacs 0x3 /* 4clk */
+#define B2_Tcos 0x3 /* 4clk */
+#define B2_Tacc 0x7 /* 14clk */
+#define B2_Tcoh 0x3 /* 4clk */
+#define B2_Tcah 0x3 /* 4clk */
+#define B2_Tacp 0x0 /* page mode is not used */
+#define B2_PMC 0x0 /* page mode disabled */
+
+/* BANK3CON 200 + 250 + 266 */
+#define B3_Tacs 0x3 /* 4clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x3 /* 4clk */
+#define B3_Tcah 0x3 /* 4clk */
+#define B3_Tacp 0x0 /* page mode is not used */
+#define B3_PMC 0x0 /* page mode disabled */
+
+/* BANK4CON 200 */
+#define B4_Tacs_200 0x1 /* 1clk */
+#define B4_Tcos_200 0x3 /* 4clk */
+#define B4_Tacc_200 0x7 /* 14clk */
+#define B4_Tcoh_200 0x3 /* 4clk */
+#define B4_Tcah_200 0x2 /* 2clk */
+#define B4_Tacp_200 0x0 /* page mode is not used */
+#define B4_PMC_200 0x0 /* page mode disabled */
+
+/* BANK4CON 250 */
+#define B4_Tacs_250 0x1 /* 1clk */
+#define B4_Tcos_250 0x3 /* 4clk */
+#define B4_Tacc_250 0x7 /* 14clk */
+#define B4_Tcoh_250 0x3 /* 4clk */
+#define B4_Tcah_250 0x2 /* 2clk */
+#define B4_Tacp_250 0x0 /* page mode is not used */
+#define B4_PMC_250 0x0 /* page mode disabled */
+
+/* BANK4CON 266 */
+#define B4_Tacs_266 0x1 /* 1clk */
+#define B4_Tcos_266 0x3 /* 4clk */
+#define B4_Tacc_266 0x7 /* 14clk */
+#define B4_Tcoh_266 0x3 /* 4clk */
+#define B4_Tcah_266 0x2 /* 2clk */
+#define B4_Tacp_266 0x0 /* page mode is not used */
+#define B4_PMC_266 0x0 /* page mode disabled */
+
+/* BANK5CON 200 */
+#define B5_Tacs_200 0x0 /* 0clk */
+#define B5_Tcos_200 0x3 /* 4clk */
+#define B5_Tacc_200 0x4 /* 6clk */
+#define B5_Tcoh_200 0x3 /* 4clk */
+#define B5_Tcah_200 0x1 /* 1clk */
+#define B5_Tacp_200 0x0 /* page mode is not used */
+#define B5_PMC_200 0x0 /* page mode disabled */
+
+/* BANK5CON 250 */
+#define B5_Tacs_250 0x0 /* 0clk */
+#define B5_Tcos_250 0x3 /* 4clk */
+#define B5_Tacc_250 0x5 /* 8clk */
+#define B5_Tcoh_250 0x3 /* 4clk */
+#define B5_Tcah_250 0x1 /* 1clk */
+#define B5_Tacp_250 0x0 /* page mode is not used */
+#define B5_PMC_250 0x0 /* page mode disabled */
+
+/* BANK5CON 266 */
+#define B5_Tacs_266 0x0 /* 0clk */
+#define B5_Tcos_266 0x3 /* 4clk */
+#define B5_Tacc_266 0x5 /* 8clk */
+#define B5_Tcoh_266 0x3 /* 4clk */
+#define B5_Tcah_266 0x1 /* 1clk */
+#define B5_Tacp_266 0x0 /* page mode is not used */
+#define B5_PMC_266 0x0 /* page mode disabled */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd_200 0x0 /* 2clk */
+#define B6_Trcd_250 0x1 /* 3clk */
+#define B6_Trcd_266 0x1 /* 3clk */
+#define B6_SCAN 0x2 /* 10bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd_200 0x0 /* 2clk */
+#define B7_Trcd_250 0x1 /* 3clk */
+#define B7_Trcd_266 0x1 /* 3clk */
+#define B7_SCAN 0x2 /* 10bit */