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at91sam9261ek.c: fix minor coding style issue.
[oweals/u-boot.git]
/
board
/
lubbock
/
lowlevel_init.S
diff --git
a/board/lubbock/lowlevel_init.S
b/board/lubbock/lowlevel_init.S
index 2a9bcbf494a069d86725a0df81a4570f0c68d280..db6f69d36ea3e7dacb2df067dd1a1a181bd3d093 100644
(file)
--- a/
board/lubbock/lowlevel_init.S
+++ b/
board/lubbock/lowlevel_init.S
@@
-29,7
+29,7
@@
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
-DRAM_SIZE: .long C
FG
_DRAM_SIZE
+DRAM_SIZE: .long C
ONFIG_SYS
_DRAM_SIZE
/* wait for coprocessor write complete */
.macro CPWAIT reg
/* wait for coprocessor write complete */
.macro CPWAIT reg
@@
-51,67
+51,67
@@
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
- ldr r1, =C
FG
_GPSR0_VAL
+ ldr r1, =C
ONFIG_SYS
_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
str r1, [r0]
ldr r0, =GPSR1
- ldr r1, =C
FG
_GPSR1_VAL
+ ldr r1, =C
ONFIG_SYS
_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
str r1, [r0]
ldr r0, =GPSR2
- ldr r1, =C
FG
_GPSR2_VAL
+ ldr r1, =C
ONFIG_SYS
_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
str r1, [r0]
ldr r0, =GPCR0
- ldr r1, =C
FG
_GPCR0_VAL
+ ldr r1, =C
ONFIG_SYS
_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
str r1, [r0]
ldr r0, =GPCR1
- ldr r1, =C
FG
_GPCR1_VAL
+ ldr r1, =C
ONFIG_SYS
_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
str r1, [r0]
ldr r0, =GPCR2
- ldr r1, =C
FG
_GPCR2_VAL
+ ldr r1, =C
ONFIG_SYS
_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
str r1, [r0]
ldr r0, =GPDR0
- ldr r1, =C
FG
_GPDR0_VAL
+ ldr r1, =C
ONFIG_SYS
_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
str r1, [r0]
ldr r0, =GPDR1
- ldr r1, =C
FG
_GPDR1_VAL
+ ldr r1, =C
ONFIG_SYS
_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
str r1, [r0]
ldr r0, =GPDR2
- ldr r1, =C
FG
_GPDR2_VAL
+ ldr r1, =C
ONFIG_SYS
_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
str r1, [r0]
ldr r0, =GAFR0_L
- ldr r1, =C
FG
_GAFR0_L_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
str r1, [r0]
ldr r0, =GAFR0_U
- ldr r1, =C
FG
_GAFR0_U_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
str r1, [r0]
ldr r0, =GAFR1_L
- ldr r1, =C
FG
_GAFR1_L_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
str r1, [r0]
ldr r0, =GAFR1_U
- ldr r1, =C
FG
_GAFR1_U_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
str r1, [r0]
ldr r0, =GAFR2_L
- ldr r1, =C
FG
_GAFR2_L_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
str r1, [r0]
ldr r0, =GAFR2_U
- ldr r1, =C
FG
_GAFR2_U_VAL
+ ldr r1, =C
ONFIG_SYS
_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =C
FG
_PSSR_VAL
+ ldr r1, =C
ONFIG_SYS
_PSSR_VAL
str r1, [r0]
/* ---------------------------------------------------------------- */
str r1, [r0]
/* ---------------------------------------------------------------- */
@@
-149,17
+149,17
@@
mem_init:
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
- ldr r2, =C
FG
_MSC0_VAL
+ ldr r2, =C
ONFIG_SYS
_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
- ldr r2, =C
FG
_MSC1_VAL
+ ldr r2, =C
ONFIG_SYS
_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2, =C
FG
_MSC2_VAL
+ ldr r2, =C
ONFIG_SYS
_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
@@
-168,37
+168,37
@@
mem_init:
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2, =C
FG
_MECR_VAL
+ ldr r2, =C
ONFIG_SYS
_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =C
FG
_MCMEM0_VAL
+ ldr r2, =C
ONFIG_SYS
_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =C
FG
_MCMEM1_VAL
+ ldr r2, =C
ONFIG_SYS
_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =C
FG
_MCATT0_VAL
+ ldr r2, =C
ONFIG_SYS
_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =C
FG
_MCATT1_VAL
+ ldr r2, =C
ONFIG_SYS
_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =C
FG
_MCIO0_VAL
+ ldr r2, =C
ONFIG_SYS
_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =C
FG
_MCIO1_VAL
+ ldr r2, =C
ONFIG_SYS
_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
@@
-214,7
+214,7
@@
mem_init:
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
- ldr r3, =C
FG
_MDREFR_VAL
+ ldr r3, =C
ONFIG_SYS
_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r4, =0x03ca4000
ldr r2, =0xFFF
and r3, r3, r2
ldr r4, =0x03ca4000
@@
-244,7
+244,7
@@
mem_init:
/* set MDREFR according to user define with exception of a few bits */
/* set MDREFR according to user define with exception of a few bits */
- ldr r4, =C
FG
_MDREFR_VAL
+ ldr r4, =C
ONFIG_SYS
_MDREFR_VAL
orr r4, r4, #(MDREFR_SLFRSH)
bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
orr r4, r4, #(MDREFR_SLFRSH)
bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
@@
-259,7
+259,7
@@
mem_init:
/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
- ldr r4, =C
FG
_MDREFR_VAL
+ ldr r4, =C
ONFIG_SYS
_MDREFR_VAL
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r4, [r1, #MDREFR_OFFSET]
@@
-267,7
+267,7
@@
mem_init:
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
- ldr r4, =C
FG
_MDCNFG_VAL
+ ldr r4, =C
ONFIG_SYS
_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
@@
-294,7
+294,7
@@
mem_init:
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
- ldr r3, =C
FG
_DRAM_BASE
+ ldr r3, =C
ONFIG_SYS
_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
@@
-314,7
+314,7
@@
mem_init:
/* Step 4h: Write MDMRS. */
/* Step 4h: Write MDMRS. */
- ldr r2, =C
FG
_MDMRS_VAL
+ ldr r2, =C
ONFIG_SYS
_MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
str r2, [r1, #MDMRS_OFFSET]