+ /* SDRAM bank 0 */
+ out_be32(&memctl->memc_mcr, 0x80002105);
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+ /* SDRAM bank 1 */
+ out_be32(&memctl->memc_mcr, 0x80004105);
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+ /* SDRAM bank 2 */
+ out_be32(&memctl->memc_mcr, 0x80006105);
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
+ udelay(1);
+ out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
+ udelay(1);
+
+ setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
+ udelay(1000);
+
+ out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+ udelay(1000);
+ if(rev >= 7) {
+ size = 32 * 3 * 1024 * 1024;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
+ out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
+ out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
+ out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
+ out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
+ out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
+ } else {
+ size = 16 * 3 * 1024 * 1024;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
+ out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
+ out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
+ out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
+ out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
+ out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
+ }
+ return (size);