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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
[oweals/u-boot.git]
/
board
/
jse
/
init.S
diff --git
a/board/jse/init.S
b/board/jse/init.S
index c564ed3c94ec36a28d2a3ccd43c53d3c19aa080b..bccc7e09927cd945b8bcd0053b08a528904644c6 100644
(file)
--- a/
board/jse/init.S
+++ b/
board/jse/init.S
@@
-1,5
+1,9
@@
/*------------------------------------------------------------------------+ */
/* */
/*------------------------------------------------------------------------+ */
/* */
+/* This source code is dual-licensed. You may use it under the terms */
+/* of the GNU General Public License version 2, or under the license */
+/* below. */
+/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
@@
-40,7
+44,7
@@
/* Bank 6 - not used */
/* Bank 7 - not used */
/*------------------------------------------------------------------------- */
/* Bank 6 - not used */
/* Bank 7 - not used */
/*------------------------------------------------------------------------- */
-#include <ppc4xx.h>
+#include <
asm/
ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@
-48,8
+52,6
@@
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/mmu.h>
-#define cpc0_cr0 0xB1
-
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
@@
-80,16
+82,16
@@
ext_bus_cntlr_init:
/* Memory Bank 0 (Flash) initialization */
/*----------------------------------------------------------------- */
/* Memory Bank 0 (Flash) initialization */
/*----------------------------------------------------------------- */
- addi r4,0,
pb0ap
- mtdcr
ebccfga
,r4
+ addi r4,0,
PB1AP
+ mtdcr
EBC0_CFGADDR
,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
addis r4,0,0x9B01
ori r4,r4,0x5480
- mtdcr
ebccfgd
,r4
+ mtdcr
EBC0_CFGDATA
,r4
- addi r4,0,
pb0cr
- mtdcr
ebccfga
,r4
+ addi r4,0,
PB0CR
+ mtdcr
EBC0_CFGADDR
,r4
addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr
ebccfgd
,r4
+ mtdcr
EBC0_CFGDATA
,r4
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