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Merge branch 'master' of git://git.denx.de/u-boot-at91
[oweals/u-boot.git]
/
board
/
freescale
/
mpc8568mds
/
tlb.c
diff --git
a/board/freescale/mpc8568mds/tlb.c
b/board/freescale/mpc8568mds/tlb.c
index 75651765fcbeedc9a0f87b3d913470ff25879667..8470c878e19bc3cc142295d3d4b67830a0e57c1e 100644
(file)
--- a/
board/freescale/mpc8568mds/tlb.c
+++ b/
board/freescale/mpc8568mds/tlb.c
@@
-28,16
+28,16
@@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR, CFG
_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS
_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 4 * 1024 , CFG
_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 8 * 1024 , CFG
_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 12 * 1024 , CFG
_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@
-47,7
+47,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xff000000 16M FLASH (upper half)
* Out of reset this entry is only 4K.
*/
* 0xff000000 16M FLASH (upper half)
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, C
FG_FLASH_BASE + 0x1000000, CFG
_FLASH_BASE + 0x1000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS
_FLASH_BASE + 0x1000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
@@
-55,7
+55,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLBe 1: 16M Non-cacheable, guarded
* 0xfe000000 16M FLASH (lower half)
*/
* TLBe 1: 16M Non-cacheable, guarded
* 0xfe000000 16M FLASH (lower half)
*/
- SET_TLB_ENTRY(1, C
FG_FLASH_BASE, CFG
_FLASH_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
@@
-64,7
+64,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
- SET_TLB_ENTRY(1, C
FG_PCI1_MEM_PHYS, CFG
_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS
_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
@@
-74,7
+74,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
- SET_TLB_ENTRY(1, C
FG_CCSRBAR, CFG
_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_CCSRBAR, CONFIG_SYS
_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
@@
-82,7
+82,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
* TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- SET_TLB_ENTRY(1, C
FG_LBC_SDRAM_BASE, CFG
_LBC_SDRAM_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS
_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
@@
-92,7
+92,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, C
FG_BCSR_BASE, CFG
_BCSR_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_BCSR_BASE, CONFIG_SYS
_BCSR_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
};