- debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
- devdisr, sdrs2_io_sel, io_sel);
-
- if (sdrs2_io_sel == 7)
- printf("Serdes2 disalbed\n");
- else if (sdrs2_io_sel == 4) {
- printf("eTSEC1 is in sgmii mode.\n");
- printf("eTSEC3 is in sgmii mode.\n");
- } else if (sdrs2_io_sel == 6)
- printf("eTSEC1 is in sgmii mode.\n");
-
- puts("\n");
-#ifdef CONFIG_PCIE3
- pcie_configured = is_serdes_configured(PCIE3);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
- set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
- LAW_TRGT_IF_PCIE_3);
- set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_3);
- SET_STD_PCIE_INFO(pci_info[num], 3);
- pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
- } else {
- printf("PCIE3: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_serdes_configured(PCIE1);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
- LAW_TRGT_IF_PCIE_1);
- set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_1);
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf("PCIE1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- pcie_configured = is_serdes_configured(PCIE2);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
- set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
- LAW_TRGT_IF_PCIE_2);
- set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_2);
- SET_STD_PCIE_INFO(pci_info[num], 2);
- pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
- } else {
- printf("PCIE2: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1