- i = im->sysconf.ddrlaw.ar;
- __asm__ __volatile__ ("isync");
-
- /* Enable DDR */
- im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
-
- /* Initialize DDR Priority Manager */
- im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
- im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
- im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
- im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
- im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
- im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
- im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
- im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
- im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
- im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
- im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
- im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
- im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
- im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
- im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
- im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
- im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
- im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
- im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
- im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
- im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
- im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
- im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
-
- /* Initialize MDDRC */
- im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
- im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
- im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
- im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
-
- /* Initialize DDR */
- for (i = 0; i < 10; i++)
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
- im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
- /* Start MDDRC */
- im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
- im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
+ ddr512x_config_t elpida_mddrc_config = {
+ .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+ .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+ .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
+ };
+
+ u32 elpida_init_sequence[] = {
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_EM3,
+ CONFIG_SYS_DDRCMD_EN_DLL,
+ CONFIG_SYS_ELPIDA_RES_DLL,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+ CONFIG_SYS_ELPIDA_OCD_EXIT,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP
+ };
+
+ if (is_micron()) {
+ msize = fixed_sdram(NULL, NULL, 0);
+ } else {
+ msize = fixed_sdram(&elpida_mddrc_config,
+ elpida_init_sequence,
+ sizeof(elpida_init_sequence)/sizeof(u32));
+ }