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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
[oweals/u-boot.git]
/
board
/
freescale
/
m547xevb
/
m547xevb.c
diff --git
a/board/freescale/m547xevb/m547xevb.c
b/board/freescale/m547xevb/m547xevb.c
index 539da78de984782b161574ab1afea1ea2fb63265..fd9bddd22fc793e4b8180955a49e63a7f44e07c4 100644
(file)
--- a/
board/freescale/m547xevb/m547xevb.c
+++ b/
board/freescale/m547xevb/m547xevb.c
@@
-2,7
+2,7
@@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007
, 2012
Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@
-28,6
+28,7
@@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
@@
-38,58
+39,59
@@
int checkboard(void)
return 0;
};
return 0;
};
-
long in
t initdram(int board_type)
+
phys_size_
t initdram(int board_type)
{
{
-
volatile
siu_t *siu = (siu_t *) (MMAP_SIU);
-
volatile sdram_t *sdram = (volatile
sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+
sdram_t *sdram = (
sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
u32 dramsize, i;
-#ifdef C
FG
_DRAMSZ1
+#ifdef C
ONFIG_SYS
_DRAMSZ1
u32 temp;
#endif
u32 temp;
#endif
-
siu->drv = CFG_SDRAM_DRVSTRENGTH
;
+
out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH)
;
- dramsize = C
FG
_DRAMSZ * 0x100000;
+ dramsize = C
ONFIG_SYS
_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
-
siu->cs0cfg = (CFG
_SDRAM_BASE | i);
+
out_be32(&siu->cs0cfg, CONFIG_SYS
_SDRAM_BASE | i);
-#ifdef C
FG
_DRAMSZ1
- temp = C
FG
_DRAMSZ1 * 0x100000;
+#ifdef C
ONFIG_SYS
_DRAMSZ1
+ temp = C
ONFIG_SYS
_DRAMSZ1 * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
-
siu->cs1cfg = ((CFG
_SDRAM_BASE + temp) | i);
+
out_be32(&siu->cs1cfg, (CONFIG_SYS
_SDRAM_BASE + temp) | i);
#endif
#endif
-
sdram->cfg1 = CFG_SDRAM_CFG1
;
-
sdram->cfg2 = CFG_SDRAM_CFG2
;
+
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1)
;
+
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2)
;
/* Issue PALL */
/* Issue PALL */
-
sdram->ctrl = CFG_SDRAM_CTRL | 2
;
+
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2)
;
/* Issue LEMR */
/* Issue LEMR */
-
sdram->mode = CFG_SDRAM_EMOD
;
-
sdram->mode = (CFG
_SDRAM_MODE | 0x04000000);
+
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD)
;
+
out_be32(&sdram->mode, CONFIG_SYS
_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
udelay(500);
/* Issue PALL */
-
sdram->ctrl = (CFG
_SDRAM_CTRL | 2);
+
out_be32(&sdram->ctrl, CONFIG_SYS
_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
/* Perform two refresh cycles */
-
sdram->ctrl = CFG_SDRAM_CTRL | 4
;
-
sdram->ctrl = CFG_SDRAM_CTRL | 4
;
+
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4)
;
+
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4)
;
-
sdram->mode = CFG_SDRAM_MODE
;
+
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE)
;
- sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
udelay(100);