+ /*
+ * Setup GPIO pins
+ */
+
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
+ CONFIG_SYS_FPGA_DONE | \
+ CONFIG_SYS_XEREADY | \
+ CONFIG_SYS_NONMONARCH | \
+ CONFIG_SYS_REV1_2) << 5));
+
+ if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+ /* rev 1.2 boards */
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
+ CONFIG_SYS_SELF_RST) << 5));
+ }
+
+ out32(GPIO0_OR, 0);
+ out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
+
+ /* - check if rev1_2 is low, then:
+ * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
+ */
+