+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Get version of PCI405 board from GPIO's
+ */
+
+ /*
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ switch (value) {
+ case 0x00100200:
+ /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+ return 1;
+ case 0x00000200:
+ /* CS2==0 && IRQ5==1 -> version 1.2 */
+ return 2;
+ case 0x00000000:
+ /* CS2==0 && IRQ5==0 -> version 1.3 */
+ return 3;
+#if 0 /* not yet manufactured ! */
+ case 0x00100000:
+ /* CS2==1 && IRQ5==0 -> version 1.4 */
+ return 4;
+#endif
+ default:
+ /* should not be reached! */
+ return 0;
+ }
+}
+
+
+unsigned long fpga_done_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_DONE_STATE_V11;
+ } else {
+ return FPGA_DONE_STATE_V12;
+ }
+}
+
+
+unsigned long fpga_init_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_INIT_STATE_V11;
+ } else {
+ return FPGA_INIT_STATE_V12;
+ }
+}
+
+
+int board_early_init_f (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /*
+ * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+ */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */