-#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+#define FPGA_CLK_LOW 0
+#define FPGA_CLK_HIGH FPGA_CLK
+
+#define FPGA_DATA_LOW 0
+#define FPGA_DATA_HIGH FPGA_DATA
+
+#define FPGA_WRITE_1 { \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */