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ppc4xx: Sequoia: Fix TLB reassignment in NAND booting code
[oweals/u-boot.git]
/
board
/
amcc
/
sequoia
/
cmd_sequoia.c
diff --git
a/board/amcc/sequoia/cmd_sequoia.c
b/board/amcc/sequoia/cmd_sequoia.c
index e7997e94db739f9d93942920c5f6a33f64711a08..6dfd8ba381fc7552064380d69cb689e2a01ae01c 100644
(file)
--- a/
board/amcc/sequoia/cmd_sequoia.c
+++ b/
board/amcc/sequoia/cmd_sequoia.c
@@
-40,13
+40,13
@@
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
- * the only
value affected for a 66MHz PCI and simply needs a +0x10
.
+ * the only
value affected for a 33MHz PCI and simply needs a | 0x08
.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
-/* check with Stefan on C
FG
_I2C_EEPROM_ADDR */
+/* check with Stefan on C
ONFIG_SYS
_I2C_EEPROM_ADDR */
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
@@
-57,6
+57,7
@@
static char *config_labels[] = {
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
};
@@
-97,6
+98,11
@@
static u8 boot_configs[][17] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
+ {
+ (NOR_COMPATIBLE),
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, 0x40,
+ 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ },
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
@@
-122,7
+128,7
@@
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
extern char console_buffer[];
if (argc < 2) {
extern char console_buffer[];
if (argc < 2) {
-
printf("Usage:\n%s\n", cmdtp->usage
);
+
cmd_usage(cmdtp
);
return 1;
}
return 1;
}
@@
-201,7
+207,7
@@
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/* check CPLD register +5 for PCI 66MHz flag */
}
/* check CPLD register +5 for PCI 66MHz flag */
- if ((in_8((void *)(C
FG_BCSR_BASE + 5)) & CFG
_BCSR5_PCI66EN) == 0)
+ if ((in_8((void *)(C
ONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS
_BCSR5_PCI66EN) == 0)
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
/*
* PLB-to-PCI divisor = 3 for 33MHz sync PCI
* instead of 2 for 66MHz systems
@@
-210,7
+216,7
@@
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
- udelay(C
FG
_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+ udelay(C
ONFIG_SYS
_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
@@
-220,6
+226,6
@@
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
- "
bootstrap - program the I2C bootstrap EEPROM\n
",
+ "
program the I2C bootstrap EEPROM
",
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);