-static u32 is_cram_inited()
-{
- volatile unsigned long spr_reg;
-
- /*
- * If CRAM is initialized already, then don't reinitialize it again.
- * In the case of NAND boot and SPI boot, CRAM will already be
- * initialized by the pre-loader
- */
- spr_reg = (volatile unsigned long) mfspr(SPRG7);
- if (spr_reg == LOAK_CRAM) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/******
- * return 0 if not CRAM
- * return 1 if CRAM and it's already inited by preloader
- * else return cram_id (CRAM Device Identification Register)
- ******/
-static u32 is_cram(void)
-{
- u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
- volatile u32 gpio_reg;
- volatile u32 cram_id = 0;
-
- if (is_cram_inited() == 1) {
- /* this is CRAM and it is already inited (by preloader) */
- cram_id = 1;
- } else {
- /*
- * # CRAM CLOCK
- * set GPIO0_TCR.G8 = 1
- * set GPIO0_OSRL.G8 = 0
- * set GPIO0_OR.G8 = 0
- */
- gpio_reg = in32(GPIO0_TCR);
- gpio_TCR = gpio_reg;
- out32(GPIO0_TCR, gpio_reg | 0x00800000);
- gpio_reg = in32(GPIO0_OSRL);
- gpio_OSRL = gpio_reg;
- out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
- gpio_reg = in32(GPIO0_OR);
- gpio_OR = gpio_reg;
- out32(GPIO0_OR, gpio_reg & 0xff7fffff);
-
- /*
- * # CRAM Addreaa Valid
- * set GPIO0_TCR.G10 = 1
- * set GPIO0_OSRL.G10 = 0
- * set GPIO0_OR.G10 = 0
- */
- gpio_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, gpio_reg | 0x00200000);
- gpio_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
- gpio_reg = in32(GPIO0_OR);
- out32(GPIO0_OR, gpio_reg & 0xffdfffff);
-
- /*
- * # config input (EBC_WAIT)
- * set GPIO0_ISR1L.G9 = 1
- * set GPIO0_TCR.G9 = 0
- */
- gpio_reg = in32(GPIO0_ISR1L);
- gpio_ISR1L = gpio_reg;
- out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
- gpio_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
-
- /*
- * Enable CRE to read Registers
- * set GPIO0_TCR.21 = 1
- * set GPIO1_OR.21 = 1
- */
- gpio_reg = in32(GPIO1_TCR);
- out32(GPIO1_TCR, gpio_reg | 0x00000400);
-
- gpio_reg = in32(GPIO1_OR);
- out32(GPIO1_OR, gpio_reg | 0x00000400);
-
- /* Read Version ID */
- cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
- udelay(100000);
-
- asm volatile(" sync");
- asm volatile(" eieio");
-
- debug("Cram ID: %X ", cram_id);
-
- switch (cram_id) {
- case MICRON_MT45W8MW16BGX_CRAM_ID:
- case MICRON_MT45W8MW16BGX_CRAM_ID2:
- /* supported CRAM vendor/part */
- break;
- case CRAM_DEVID_NOT_SUPPORTED:
- default:
- /* check for DIDR Vendor ID of Micron */
- if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
- MICRON_DIDR_VENDOR_ID)
- {
- /* supported CRAM vendor */
- break;
- }
- /* this is not CRAM or not supported CRAM vendor/part */
- cram_id = 0;
- /*
- * reset the GPIO registers to the values that were
- * there before this routine
- */
- out32(GPIO0_TCR, gpio_TCR);
- out32(GPIO0_OSRL, gpio_OSRL);
- out32(GPIO0_OR, gpio_OR);
- out32(GPIO0_ISR1L, gpio_ISR1L);
- break;
- }
- }
-
- return cram_id;
-}
-
-static long int cram_init(u32 already_inited)
-{
- volatile u32 tmp_reg;
- u32 cram_wr_val;
-
- if (already_inited == 0) return 0;
-
- /*
- * If CRAM is initialized already, then don't reinitialize it again.
- * In the case of NAND boot and SPI boot, CRAM will already be
- * initialized by the pre-loader
- */
- if (already_inited != 1) {
- /*
- * #o CRAM Card
- * # - CRAMCRE @reg16 = 1; for CRAM to use
- * # - CRAMCRE @reg16 = 0; for CRAM to program
- *
- * # enable CRAM SEL, move from setEPLD.cmd
- * set EPLD0_MUX_CTL.OECRAM = 0
- * set EPLD0_MUX_CTL.CRAMCR = 1
- * set EPLD0_ETHRSTBOOT.SLCRAM = 0
- * #end
- */
-
- /*
- * #1. EBC need to program READY, CLK, ADV for ASync mode
- * # config output
- */
-
- /*
- * # CRAM CLOCK
- * set GPIO0_TCR.G8 = 1
- * set GPIO0_OSRL.G8 = 0
- * set GPIO0_OR.G8 = 0
- */
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg | 0x00800000);
- tmp_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
- tmp_reg = in32(GPIO0_OR);
- out32(GPIO0_OR, tmp_reg & 0xff7fffff);
-
- /*
- * # CRAM Addreaa Valid
- * set GPIO0_TCR.G10 = 1
- * set GPIO0_OSRL.G10 = 0
- * set GPIO0_OR.G10 = 0
- */
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg | 0x00200000);
- tmp_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
- tmp_reg = in32(GPIO0_OR);
- out32(GPIO0_OR, tmp_reg & 0xffdfffff);
-
- /*
- * # config input (EBC_WAIT)
- * set GPIO0_ISR1L.G9 = 1
- * set GPIO0_TCR.G9 = 0
- */
- tmp_reg = in32(GPIO0_ISR1L);
- out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
-
- /*
- * # config CS4 from GPIO
- * set GPIO0_TCR.G0 = 1
- * set GPIO0_OSRL.G0 = 1
- */
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg | 0x80000000);
- tmp_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, tmp_reg | 0x40000000);
-
- /*
- * #2. EBC in Async mode
- * # set EBC0_PB1AP = 0x078f0ec0
- * set EBC0_PB1AP = 0x078f1ec0
- * set EBC0_PB2AP = 0x078f1ec0
- */
- mtebc(pb1ap, 0x078F1EC0);
- mtebc(pb2ap, 0x078F1EC0);
-
- /*
- * #set EBC0_PB1CR = 0x000bc000
- * #enable CS2 for CRAM
- * set EBC0_PB2CR = 0x020bc000
- */
- mtebc(pb1cr, 0x000BC000);
- mtebc(pb2cr, 0x020BC000);
-
- /*
- * #3. set CRAM in Sync mode
- * #exec cm_bcr_write.cmd { 0x701f }
- * #3. set CRAM in Sync mode (full drv strength)
- * exec cm_bcr_write.cmd { 0x701F }
- */
- cram_wr_val = 0x7012; /* CRAM burst setting */
- cram_bcr_write(cram_wr_val);
-
- /*
- * #4. EBC in Sync mode
- * #set EBC0_PB1AP = 0x9f800fc0
- * #set EBC0_PB1AP = 0x900001c0
- * set EBC0_PB2AP = 0x9C0201c0
- * set EBC0_PB2AP = 0x9C0201c0
- */
- mtebc(pb1ap, 0x9C0201C0);
- mtebc(pb2ap, 0x9C0201C0);
-
- /*
- * #5. EBC need to program READY, CLK, ADV for Sync mode
- * # config output
- * set GPIO0_TCR.G8 = 1
- * set GPIO0_OSRL.G8 = 1
- * set GPIO0_TCR.G10 = 1
- * set GPIO0_OSRL.G10 = 1
- */
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg | 0x00800000);
- tmp_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, tmp_reg | 0x00004000);
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg | 0x00200000);
- tmp_reg = in32(GPIO0_OSRL);
- out32(GPIO0_OSRL, tmp_reg | 0x00000400);
-
- /*
- * # config input
- * set GPIO0_ISR1L.G9 = 1
- * set GPIO0_TCR.G9 = 0
- */
- tmp_reg = in32(GPIO0_ISR1L);
- out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
- tmp_reg = in32(GPIO0_TCR);
- out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
-
- /*
- * # config EBC to use RDY
- * set SDR0_ULTRA0.EBCREN = 1
- */
- mfsdr(sdrultra0, tmp_reg);
- mtsdr(sdrultra0, tmp_reg | 0x04000000);
-
- /*
- * set EPLD0_MUX_CTL.OESPR3 = 0
- */
- mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
- } /* if (already_inited != 1) */
-
- return (64 * 1024 * 1024);
-}
-
-/******
- * return 0 if not PSRAM
- * return 1 if is PSRAM
- ******/
-static int is_psram(u32 addr)