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CHECKPATCH: arch/x86/lib/*
[oweals/u-boot.git]
/
arch
/
x86
/
lib
/
pci_type1.c
diff --git
a/arch/x86/lib/pci_type1.c
b/arch/x86/lib/pci_type1.c
index da1d3566ad525882b526b78223c5725b1aa12d60..a25fa051d50fd64209e44242817522231d28dbdb 100644
(file)
--- a/
arch/x86/lib/pci_type1.c
+++ b/
arch/x86/lib/pci_type1.c
@@
-29,7
+29,7
@@
#include <asm/io.h>
#include <pci.h>
#include <asm/io.h>
#include <pci.h>
-#define cfg_read(val, addr, op)
*val = op((int)(addr
))
+#define cfg_read(val, addr, op)
(*val = op((int)(addr)
))
#define cfg_write(val, addr, op) op((val), (int)(addr))
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
#define cfg_write(val, addr, op) op((val), (int)(addr))
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
@@
-42,7
+42,6
@@
type1_##rw##_config_##size(struct pci_controller *hose, \
return 0; \
}
return 0; \
}
-
TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
TYPE1_PCI_OP(read, word, u16 *, inw, 2)
TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
TYPE1_PCI_OP(read, word, u16 *, inw, 2)
TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
@@
-51,7
+50,11
@@
TYPE1_PCI_OP(write, byte, u8, outb, 3)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
-void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+/* bus mapping constants (used for PCI core initialization) */
+#define PCI_REG_ADDR 0x00000cf8
+#define PCI_REG_DATA 0x00000cfc
+
+void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,
type1_read_config_byte,
{
pci_set_ops(hose,
type1_read_config_byte,
@@
-61,6
+64,6
@@
void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
type1_write_config_word,
type1_write_config_dword);
type1_write_config_word,
type1_write_config_dword);
- hose->cfg_addr = (unsigned int *)
cfg_addr
;
- hose->cfg_data = (unsigned char *)
cfg_data
;
+ hose->cfg_addr = (unsigned int *)
PCI_REG_ADDR
;
+ hose->cfg_data = (unsigned char *)
PCI_REG_DATA
;
}
}