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x86: fsp_support: Correct high mem comment typo
[oweals/u-boot.git]
/
arch
/
x86
/
lib
/
pci_type1.c
diff --git
a/arch/x86/lib/pci_type1.c
b/arch/x86/lib/pci_type1.c
index 13942a33f73b18088d3dc40dfb00865ca2dd3eff..a251adcacd41cf0252f3145706ebb64f24ead2b0 100644
(file)
--- a/
arch/x86/lib/pci_type1.c
+++ b/
arch/x86/lib/pci_type1.c
@@
-12,6
+12,7
@@
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <asm/io.h>
#include <pci.h>
+#include <asm/pci.h>
#define cfg_read(val, addr, op) (*val = op((int)(addr)))
#define cfg_write(val, addr, op) op((val), (int)(addr))
#define cfg_read(val, addr, op) (*val = op((int)(addr)))
#define cfg_write(val, addr, op) op((val), (int)(addr))
@@
-21,7
+22,7
@@
static int \
type1_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
type1_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
- outl(dev | (offset & 0xfc) |
0x80000000
, (int)hose->cfg_addr); \
+ outl(dev | (offset & 0xfc) |
PCI_CFG_EN
, (int)hose->cfg_addr); \
cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
return 0; \
}
cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
return 0; \
}
@@
-34,10
+35,6
@@
TYPE1_PCI_OP(write, byte, u8, outb, 3)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
-/* bus mapping constants (used for PCI core initialization) */
-#define PCI_REG_ADDR 0x00000cf8
-#define PCI_REG_DATA 0x00000cfc
-
void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,
void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,