-static const char *const ecc_decoder[] = {
- "inactive",
- "active on IO",
- "disabled on IO",
- "active"
-};
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-static void report_memory_config(void)
-{
- u32 addr_decoder_common, addr_decode_ch[2];
- int i;
-
- addr_decoder_common = readl(MCHBAR_REG(0x5000));
- addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
- addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
-
- debug("memcfg DDR3 clock %d MHz\n",
- (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
- debug("memcfg channel assignment: A: %d, B % d, C % d\n",
- addr_decoder_common & 3,
- (addr_decoder_common >> 2) & 3,
- (addr_decoder_common >> 4) & 3);
-
- for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
- u32 ch_conf = addr_decode_ch[i];
- debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
- debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
- debug(" enhanced interleave mode %s\n",
- ((ch_conf >> 22) & 1) ? "on" : "off");
- debug(" rank interleave %s\n",
- ((ch_conf >> 21) & 1) ? "on" : "off");
- debug(" DIMMA %d MB width x%d %s rank%s\n",
- ((ch_conf >> 0) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? 16 : 8,
- ((ch_conf >> 17) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? "" : ", selected");
- debug(" DIMMB %d MB width x%d %s rank%s\n",
- ((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 20) & 1) ? 16 : 8,
- ((ch_conf >> 18) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? ", selected" : "");
- }
-}
-
-static void post_system_agent_init(struct pei_data *pei_data)