+
+/* Define these functions to allow ehch-hcd to function */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void dcache_enable(void)
+{
+ enable_caches();
+}
+
+void dcache_disable(void)
+{
+ disable_caches();
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 1;
+}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool can_detect_long_mode(void)
+{
+ return cpuid_eax(0x80000000) > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+const char *cpu_vendor_name(int vendor)
+{
+ const char *name;
+ name = "<invalid cpu vendor>";
+ if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
+ (x86_vendor_name[vendor] != 0))
+ name = x86_vendor_name[vendor];
+
+ return name;
+}
+
+char *cpu_get_name(char *name)
+{
+ unsigned int *name_as_ints = (unsigned int *)name;
+ struct cpuid_result regs;
+ char *ptr;
+ int i;
+
+ /* This bit adds up to 48 bytes */
+ for (i = 0; i < 3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i * 4 + 0] = regs.eax;
+ name_as_ints[i * 4 + 1] = regs.ebx;
+ name_as_ints[i * 4 + 2] = regs.ecx;
+ name_as_ints[i * 4 + 3] = regs.edx;
+ }
+ name[CPU_MAX_NAME_LEN - 1] = '\0';
+
+ /* Skip leading spaces. */
+ ptr = name;
+ while (*ptr == ' ')
+ ptr++;
+
+ return ptr;
+}
+
+int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+int default_print_cpuinfo(void)
+{
+ printf("CPU: %s, vendor %s, device %xh\n",
+ cpu_has_64bit() ? "x86_64" : "x86",
+ cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
+
+ return 0;
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++) {
+ pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+ 0x1000 * i + 7;
+ }
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
+
+void show_boot_progress(int val)
+{
+#if MIN_PORT80_KCLOCKS_DELAY
+ /*
+ * Scale the time counter reading to avoid using 64 bit arithmetics.
+ * Can't use get_timer() here becuase it could be not yet
+ * initialized or even implemented.
+ */
+ if (!gd->arch.tsc_prev) {
+ gd->arch.tsc_base_kclocks = rdtsc() / 1000;
+ gd->arch.tsc_prev = 0;
+ } else {
+ uint32_t now;
+
+ do {
+ now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
+ } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
+ gd->arch.tsc_prev = now;
+ }
+#endif
+ outb(val, POST_PORT);
+}
+
+#ifndef CONFIG_SYS_COREBOOT
+int last_stage_init(void)
+{
+ write_tables();
+
+ return 0;
+}
+#endif
+
+__weak int x86_init_cpus(void)
+{
+ return 0;
+}
+
+int cpu_init_r(void)
+{
+ return x86_init_cpus();
+}
+
+static const struct cpu_ops cpu_x86_ops = {
+ .get_desc = x86_cpu_get_desc,
+};
+
+static const struct udevice_id cpu_x86_ids[] = {
+ { .compatible = "cpu-x86" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_drv) = {
+ .name = "cpu_x86",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_ids,
+ .ops = &cpu_x86_ops,
+};