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Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
[oweals/u-boot.git]
/
arch
/
powerpc
/
include
/
asm
/
cache.h
diff --git
a/arch/powerpc/include/asm/cache.h
b/arch/powerpc/include/asm/cache.h
index 53e8d05f50b1a251484e8be719ab216350e1c6b5..5f9c640aa2aff83a4d43cb1a62e1d65b464b7075 100644
(file)
--- a/
arch/powerpc/include/asm/cache.h
+++ b/
arch/powerpc/include/asm/cache.h
@@
-8,7
+8,7
@@
#include <asm/processor.h>
/* bytes per L1 cache line */
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx)
|| defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
@@
-20,6
+20,12
@@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/