+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };