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env: Rename getenv_hex(), getenv_yesno(), getenv_ulong()
[oweals/u-boot.git]
/
arch
/
powerpc
/
cpu
/
mpc85xx
/
start.S
diff --git
a/arch/powerpc/cpu/mpc85xx/start.S
b/arch/powerpc/cpu/mpc85xx/start.S
index 932216c237f9d2a8b96905027018f5d51a55fc23..0f016f037028af6856d9969db8c1e2abd3a8759a 100644
(file)
--- a/
arch/powerpc/cpu/mpc85xx/start.S
+++ b/
arch/powerpc/cpu/mpc85xx/start.S
@@
-1145,8
+1145,9
@@
switch_as:
li r0,0
1:
dcbz r0,r3
li r0,0
1:
dcbz r0,r3
-#ifdef CONFIG_E6500 /* Lock/unlock L2 cache
instead of
L1 */
+#ifdef CONFIG_E6500 /* Lock/unlock L2 cache
long with
L1 */
dcbtls 2, r0, r3
dcbtls 2, r0, r3
+ dcbtls 0, r0, r3
#else
dcbtls 0, r0, r3
#endif
#else
dcbtls 0, r0, r3
#endif
@@
-1182,14
+1183,13
@@
_start_cont:
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* Leave 16+ byte for back chain termination and NULL return address */
#endif
/* Leave 16+ byte for back chain termination and NULL return address */
- subi r3,r3,((CONFIG_
SYS_MALLOC_F_LEN
+16+15)&~0xf)
+ subi r3,r3,((CONFIG_
VAL(SYS_MALLOC_F_LEN)
+16+15)&~0xf)
#endif
/* End of RAM */
#endif
/* End of RAM */
@@
-1203,7
+1203,7
@@
_start_cont:
cmplw r4,r3
bne 1b
cmplw r4,r3
bne 1b
-#if
def CONFIG_SYS_MALLOC_F_LEN
+#if
CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
@@
-1373,8
+1373,8
@@
icache_enable:
mtlr r8
isync
mfspr r4,L1CSR1
mtlr r8
isync
mfspr r4,L1CSR1
- ori r4,r4,
0x0001
- oris r4,r4,
0x0001
+ ori r4,r4,
(L1CSR1_CPE | L1CSR1_ICE)@l
+ oris r4,r4,
(L1CSR1_CPE | L1CSR1_ICE)@h
mtspr L1CSR1,r4
isync
blr
mtspr L1CSR1,r4
isync
blr
@@
-1402,8
+1402,8
@@
dcache_enable:
mtlr r8
isync
mfspr r0,L1CSR0
mtlr r8
isync
mfspr r0,L1CSR0
- ori r0,r0,
0x0001
- oris r0,r0,
0x0001
+ ori r0,r0,
(L1CSR0_CPE | L1CSR0_DCE)@l
+ oris r0,r0,
(L1CSR0_CPE | L1CSR0_DCE)@h
msync
isync
mtspr L1CSR0,r0
msync
isync
mtspr L1CSR0,r0
@@
-1426,16
+1426,6
@@
dcache_status:
andi. r3,r3,L1CSR0_DCE
blr
andi. r3,r3,L1CSR0_DCE
blr
- .globl get_pvr
-get_pvr:
- mfspr r3,PVR
- blr
-
- .globl get_svr
-get_svr:
- mfspr r3,SVR
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
@@
-1790,8
+1780,9
@@
unlock_ram_in_cache:
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
-#ifdef CONFIG_E6500 /* lock/unlock L2 cache
instead of
L1 */
+#ifdef CONFIG_E6500 /* lock/unlock L2 cache
long with
L1 */
dcblc 2, r0, r3
dcblc 2, r0, r3
+ dcblc 0, r0, r3
#else
dcblc r0,r3
#endif
#else
dcblc r0,r3
#endif