+ cplx_pll += cc_group[cluster] - 1;
+ sys_info->freq_processor[cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
+ defined(CONFIG_PPC_T2081)
+#define FM1_CLK_SEL 0xe0000000
+#define FM1_CLK_SHIFT 29
+#else
+#define PME_CLK_SEL 0xe0000000
+#define PME_CLK_SHIFT 29
+#define FM1_CLK_SEL 0x1c000000
+#define FM1_CLK_SHIFT 26
+#endif
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+#ifndef CONFIG_PME_PLAT_CLK_DIV
+ switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
+ break;
+ case 2:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
+ break;
+ case 4:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
+ break;
+ case 6:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
+ break;
+ case 7:
+ sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
+ break;
+ default:
+ printf("Error: Unknown PME clock select!\n");
+ case 0:
+ sys_info->freq_pme = sys_info->freq_systembus / 2;
+ break;
+
+ }
+#else
+ sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
+
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sys_info->freq_qman = sys_info->freq_systembus / 2;
+#endif