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Merge git://git.denx.de/u-boot-tegra
[oweals/u-boot.git]
/
arch
/
powerpc
/
cpu
/
mpc85xx
/
cpu.c
diff --git
a/arch/powerpc/cpu/mpc85xx/cpu.c
b/arch/powerpc/cpu/mpc85xx/cpu.c
index 192634d41cd7ceef98700d05025f58d989ee5bcd..bf48836036b89ff4c1d2d4ae06c12487dd8b6305 100644
(file)
--- a/
arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/
arch/powerpc/cpu/mpc85xx/cpu.c
@@
-1,3
+1,4
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
/*
* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
@@
-5,8
+6,6
@@
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
*/
#include <config.h>
@@
-23,6
+22,7
@@
#include <post.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <post.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
+#include <asm/ppc.h>
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
@@
-384,7
+384,7
@@
int cpu_mmc_init(bd_t *bis)
* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
* parameters for IFC and TLBs
*/
* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
* parameters for IFC and TLBs
*/
-void
mpc85xx
_reginfo(void)
+void
print
_reginfo(void)
{
print_tlbcam();
print_laws();
{
print_tlbcam();
print_laws();
@@
-401,17
+401,19
@@
void mpc85xx_reginfo(void)
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-
phys_size_t initdram
(void)
+
int dram_init
(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
-
return
fsl_ddr_sdram_size();
+
gd->ram_size =
fsl_ddr_sdram_size();
#else
#else
-
return
(phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
gd->ram_size =
(phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#endif
+
+ return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
}
#else /* CONFIG_SYS_RAMBOOT */
-
phys_size_t initdram
(void)
+
int dram_init
(void)
{
phys_size_t dram_size = 0;
{
phys_size_t dram_size = 0;
@@
-460,7
+462,9
@@
phys_size_t initdram(void)
#endif
debug("DDR: ");
#endif
debug("DDR: ");
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif