-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
- /* clear tag to invalidate */
- cache_loop t0, t1, a2, INDEX_STORE_TAG_I
- /* fill once, so data field parity is correct */
- PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, a2, FILL
- /* invalidate again - prudent but not strictly neccessary */
- PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, a2, INDEX_STORE_TAG_I
-9: jr ra
- END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
- /* clear all tags */
- cache_loop t0, t1, a2, INDEX_STORE_TAG_D
- /* load from each line (in cached space) */
- PTR_LI t0, INDEX_BASE
-2: LONG_L zero, 0(t0)
- PTR_ADDU t0, a2
- bne t0, t1, 2b
- /* clear all tags */
- PTR_LI t0, INDEX_BASE
- cache_loop t0, t1, a2, INDEX_STORE_TAG_D
-9: jr ra
- END(mips_init_dcache)
-