- const void *addr = (const void *)(start_addr & ~(lsize - 1));
- const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
-
- while (1) {
- mips_cache(HIT_INVALIDATE_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
+ unsigned long slsize = scache_line_size();
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (start_addr == stop)
+ return;
+
+ /* invalidate L2 cache */
+ cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD);
+
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
+
+ /* ensure cache ops complete before any further memory accesses */
+ sync();
+}
+
+int dcache_status(void)
+{
+ unsigned int cca = read_c0_config() & CONF_CM_CMASK;
+ return cca != CONF_CM_UNCACHED;
+}
+
+void dcache_enable(void)
+{
+ puts("Not supported!\n");
+}
+
+void dcache_disable(void)
+{
+ /* change CCA to uncached */
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+ /* ensure the pipeline doesn't contain now-invalid instructions */
+ instruction_hazard_barrier();