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bmips: enable vr-3032u nand support
[oweals/u-boot.git]
/
arch
/
mips
/
Kconfig
diff --git
a/arch/mips/Kconfig
b/arch/mips/Kconfig
index 9cf8e9800d8305361c54dc70dd2d8bd43e072084..f5d81b822c48d5500cf805a3ae7e8c311737f379 100644
(file)
--- a/
arch/mips/Kconfig
+++ b/
arch/mips/Kconfig
@@
-84,7
+84,7
@@
config ARCH_MTMIPS
select DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
select DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
- select
ARCH_MISC
_INIT
+ select
LAST_STAGE
_INIT
select MIPS_TUNE_24KC
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_24KC
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
@@
-408,9
+408,17
@@
config SYS_ICACHE_LINE_SIZE
help
The size of L1 Icache lines, if known at compile time.
help
The size of L1 Icache lines, if known at compile time.
+config SYS_SCACHE_LINE_SIZE
+ int
+ default 0
+ help
+ The size of L2 cache lines, if known at compile time.
+
+
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
- SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+ SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
+ SYS_SCACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes