+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
+#endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+ scm_t *scm = (scm_t *) MMAP_SCM;
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ /* Disable Switch */
+ *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+ /* Disable core watchdog */
+ out_be16(&scm->cwcr, 0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+ GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+ GPIO_PAR_FBCTL_TA_TA);
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+ /* eDMA */
+ out_8(&pm->pmcr0, 17);
+
+ /* INTR0 - INTR2 */
+ out_8(&pm->pmcr0, 18);
+ out_8(&pm->pmcr0, 19);
+ out_8(&pm->pmcr0, 20);
+
+ /* I2C */
+ out_8(&pm->pmcr0, 22);
+ out_8(&pm->pmcr1, 4);
+ out_8(&pm->pmcr1, 7);
+
+ /* DTMR0 - DTMR3*/
+ out_8(&pm->pmcr0, 28);
+ out_8(&pm->pmcr0, 29);
+ out_8(&pm->pmcr0, 30);
+ out_8(&pm->pmcr0, 31);
+
+ /* PIT0 - PIT3 */
+ out_8(&pm->pmcr0, 32);
+ out_8(&pm->pmcr0, 33);
+ out_8(&pm->pmcr0, 34);
+ out_8(&pm->pmcr0, 35);
+
+ /* Edge Port */
+ out_8(&pm->pmcr0, 36);
+ out_8(&pm->pmcr0, 37);
+
+ /* USB OTG */
+ out_8(&pm->pmcr0, 44);
+ /* USB Host */
+ out_8(&pm->pmcr0, 45);
+
+ /* ESDHC */
+ out_8(&pm->pmcr0, 51);
+
+ /* ENET0 - ENET1 */
+ out_8(&pm->pmcr0, 53);
+ out_8(&pm->pmcr0, 54);
+
+ /* NAND */
+ out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+ out_8(&gpio->par_cani2c, 0xF0);
+ /* I2C0 pull up */
+ out_be16(&gpio->pcr_b, 0x003C);
+ /* I2C0 max speed */
+ out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+ /* I2C2 */
+ out_8(&gpio->par_ssi0h, 0xA0);
+ /* I2C2, UART7 */
+ out_8(&gpio->par_ssi0h, 0xA8);
+ /* UART7 */
+ out_8(&gpio->par_ssi0l, 0x2);
+ /* UART8, UART9 */
+ out_8(&gpio->par_cani2c, 0xAA);
+ /* UART4, UART0 */
+ out_8(&gpio->par_uart0, 0xAF);
+ /* UART5, UART1 */
+ out_8(&gpio->par_uart1, 0xAF);
+ /* UART6, UART2 */
+ out_8(&gpio->par_uart2, 0xAF);
+ /* I2C2 pull up */
+ out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+ /* I2C5 */
+ out_8(&gpio->par_uart1, 0x0A);
+ /* I2C5 pull up */
+ out_be16(&gpio->pcr_e, 0x0003);
+ out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+ /* Lowest slew rate for UART0,1,2 */
+ out_8(&gpio->srcr_uart, 0x00);
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+
+ /* FlexBus */
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_SYS_FSL_I2C
+ out_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);