+struct uniphier_memif_data {
+ unsigned int soc_id;
+ unsigned long sparse_ch1_base;
+ int have_ch2;
+};
+
+static const struct uniphier_memif_data uniphier_memif_data[] = {
+ {
+ .soc_id = UNIPHIER_SLD3_ID,
+ .sparse_ch1_base = 0xc0000000,
+ /*
+ * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
+ * and ch2 overlap, and host cannot get access to them at the
+ * same time. Hide the ch2 from U-Boot.
+ */
+ },
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .sparse_ch1_base = 0xa0000000,
+ },
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PRO5_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .sparse_ch1_base = 0xc0000000,
+ },
+ {
+ .soc_id = UNIPHIER_LD20_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+ {
+ .soc_id = UNIPHIER_PXS3_ID,
+ .sparse_ch1_base = 0xc0000000,
+ .have_ch2 = 1,
+ },
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
+
+static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)