-#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
- ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
-
-void socfpga_reset_uart(int assert)
-{
- unsigned int com_port;
-
- com_port = uart_com_port(gd->fdt_blob);
-
- if (com_port == SOCFPGA_UART1_ADDRESS)
- socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
- else if (com_port == SOCFPGA_UART0_ADDRESS)
- socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
-}
-
-static const u32 per0fpgamasks[] = {
- ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
- ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
- ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
- 0, /* i2c0 per1mod */
- 0, /* i2c1 per1mod */
- 0, /* i2c0_emac */
- 0, /* i2c1_emac */
- 0, /* i2c2_emac */
- ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
- ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
- ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
- ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
- 0, /* uart0 per1mod */
- 0, /* uart1 per1mod */
-};
-
-static const u32 per1fpgamasks[] = {
- 0, /* emac0 per0mod */
- 0, /* emac1 per0mod */
- 0, /* emac2 per0mod */
- ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
- ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
- ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
- ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
- ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
- 0, /* nand per0mod */
- 0, /* qspi per0mod */
- 0, /* sdmmc per0mod */
- 0, /* spim0 per0mod */
- 0, /* spim1 per0mod */
- 0, /* spis0 per0mod */
- 0, /* spis1 per0mod */
- ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
- ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
-};
-